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Area-efficient high-speed 3D DWT processor architecture

Research output: Contribution to Journal/Magazine › Journal article › peer-review

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Area-efficient high-speed 3D DWT processor architecture. / Jiang, M.; Crookes, D.
In: Electronics Letters, Vol. 43, No. 9, 26.04.2007, p. 502-503.

Research output: Contribution to Journal/Magazine › Journal article › peer-review

Harvard

Jiang, M & Crookes, D 2007, 'Area-efficient high-speed 3D DWT processor architecture', Electronics Letters, vol. 43, no. 9, pp. 502-503. https://doi.org/10.1049/el:20070201

APA

Jiang, M., & Crookes, D. (2007). Area-efficient high-speed 3D DWT processor architecture. Electronics Letters, 43(9), 502-503. https://doi.org/10.1049/el:20070201

Vancouver

Jiang M, Crookes D. Area-efficient high-speed 3D DWT processor architecture. Electronics Letters. 2007 Apr 26;43(9):502-503. doi: 10.1049/el:20070201

Author

Jiang, M. ; Crookes, D. / Area-efficient high-speed 3D DWT processor architecture. In: Electronics Letters. 2007 ; Vol. 43, No. 9. pp. 502-503.

Bibtex

@article{f9d7c643ac574cbc99483576698121b0,
title = "Area-efficient high-speed 3D DWT processor architecture",
abstract = "An area-efficient high-throughput architecture based on distributed arithmetic is proposed for 3D discrete wavelet transform (DWT). The 3D DWT processor was designed in VHDL and mapped to a Xilinx Virtex-E FPGA. The processor runs up to 85 MHz, which can process the five-level DWT analysis of a 128times128times128 fMRI volume image in 20 ms",
keywords = "HIgh-speed 3D DWT processor, distributed arithmetic, 3D discrete wavelet transform, VHDL, Xilinx Virtex-E FPGA, five-level DWT analysis, fMRI image",
author = "M. Jiang and D. Crookes",
year = "2007",
month = apr,
day = "26",
doi = "10.1049/el:20070201",
language = "English",
volume = "43",
pages = "502--503",
journal = "Electronics Letters",
issn = "0013-5194",
publisher = "Institution of Engineering and Technology",
number = "9",

}

RIS

TY - JOUR

T1 - Area-efficient high-speed 3D DWT processor architecture

AU - Jiang, M.

AU - Crookes, D.

PY - 2007/4/26

Y1 - 2007/4/26

N2 - An area-efficient high-throughput architecture based on distributed arithmetic is proposed for 3D discrete wavelet transform (DWT). The 3D DWT processor was designed in VHDL and mapped to a Xilinx Virtex-E FPGA. The processor runs up to 85 MHz, which can process the five-level DWT analysis of a 128times128times128 fMRI volume image in 20 ms

AB - An area-efficient high-throughput architecture based on distributed arithmetic is proposed for 3D discrete wavelet transform (DWT). The 3D DWT processor was designed in VHDL and mapped to a Xilinx Virtex-E FPGA. The processor runs up to 85 MHz, which can process the five-level DWT analysis of a 128times128times128 fMRI volume image in 20 ms

KW - HIgh-speed 3D DWT processor

KW - distributed arithmetic

KW - 3D discrete wavelet transform

KW - VHDL

KW - Xilinx Virtex-E FPGA

KW - five-level DWT analysis

KW - fMRI image

U2 - 10.1049/el:20070201

DO - 10.1049/el:20070201

M3 - Journal article

VL - 43

SP - 502

EP - 503

JO - Electronics Letters

JF - Electronics Letters

SN - 0013-5194

IS - 9

ER -