Home > Research > Publications & Outputs > Clock switching

Research

Associated organisational unit

Links

Text available via DOI:

View graph of relations

Clock switching: a new design for current test (DcT) method for dynamic logic circuits

Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Conference contribution/Paper › peer-review

Published

Standard

Clock switching: a new design for current test (DcT) method for dynamic logic circuits. / Rosing, R.; Richardson, A. M. D.; Kerkhoff, A. et al.
IDDQ Testing, 1998. Proceedings. 1998 IEEE International Workshop on. IEEE, 1998. p. 20-25.

Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Conference contribution/Paper › peer-review

Harvard

Rosing, R, Richardson, AMD, Kerkhoff, A & Acosta, A 1998, Clock switching: a new design for current test (DcT) method for dynamic logic circuits. in IDDQ Testing, 1998. Proceedings. 1998 IEEE International Workshop on. IEEE, pp. 20-25. https://doi.org/10.1109/IDDQ.1998.730727

APA

Rosing, R., Richardson, A. M. D., Kerkhoff, A., & Acosta, A. (1998). Clock switching: a new design for current test (DcT) method for dynamic logic circuits. In IDDQ Testing, 1998. Proceedings. 1998 IEEE International Workshop on (pp. 20-25). IEEE. https://doi.org/10.1109/IDDQ.1998.730727

Vancouver

Rosing R, Richardson AMD, Kerkhoff A, Acosta A. Clock switching: a new design for current test (DcT) method for dynamic logic circuits. In IDDQ Testing, 1998. Proceedings. 1998 IEEE International Workshop on. IEEE. 1998. p. 20-25 doi: 10.1109/IDDQ.1998.730727

Author

Rosing, R. ; Richardson, A. M. D. ; Kerkhoff, A. et al. / Clock switching : a new design for current test (DcT) method for dynamic logic circuits. IDDQ Testing, 1998. Proceedings. 1998 IEEE International Workshop on. IEEE, 1998. pp. 20-25

Bibtex

@inproceedings{0ccc4a30d91647bba7f69bfe0dee0373,
title = "Clock switching: a new design for current test (DcT) method for dynamic logic circuits",
abstract = "Using an Iddq test methodology on circuits with dynamic logic tends to be problematic, mainly due to charge leakage related problems. A new Design for current Testability (DcT) method has been developed, which overcomes these problems by switching the circuit into a static mode during test. The method referred to as clock switching is applicable to both domino logic and True Single-Phase Clock (TSPC) circuits. This paper shows that this technique can lead to higher levels of Iddq testability and a reduced test vector set for the detection of bridging faults",
author = "R. Rosing and Richardson, {A. M. D.} and A. Kerkhoff and A. Acosta",
year = "1998",
doi = "10.1109/IDDQ.1998.730727",
language = "English",
isbn = "0818691913",
pages = "20--25",
booktitle = "IDDQ Testing, 1998. Proceedings. 1998 IEEE International Workshop on",
publisher = "IEEE",

}

RIS

TY - GEN

T1 - Clock switching

T2 - a new design for current test (DcT) method for dynamic logic circuits

AU - Rosing, R.

AU - Richardson, A. M. D.

AU - Kerkhoff, A.

AU - Acosta, A.

PY - 1998

Y1 - 1998

N2 - Using an Iddq test methodology on circuits with dynamic logic tends to be problematic, mainly due to charge leakage related problems. A new Design for current Testability (DcT) method has been developed, which overcomes these problems by switching the circuit into a static mode during test. The method referred to as clock switching is applicable to both domino logic and True Single-Phase Clock (TSPC) circuits. This paper shows that this technique can lead to higher levels of Iddq testability and a reduced test vector set for the detection of bridging faults

AB - Using an Iddq test methodology on circuits with dynamic logic tends to be problematic, mainly due to charge leakage related problems. A new Design for current Testability (DcT) method has been developed, which overcomes these problems by switching the circuit into a static mode during test. The method referred to as clock switching is applicable to both domino logic and True Single-Phase Clock (TSPC) circuits. This paper shows that this technique can lead to higher levels of Iddq testability and a reduced test vector set for the detection of bridging faults

U2 - 10.1109/IDDQ.1998.730727

DO - 10.1109/IDDQ.1998.730727

M3 - Conference contribution/Paper

SN - 0818691913

SP - 20

EP - 25

BT - IDDQ Testing, 1998. Proceedings. 1998 IEEE International Workshop on

PB - IEEE

ER -