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Demonstration of a Fast, Low-Voltage, III-V Semiconductor, Non-Volatile Memory. / Lane, Dominic; Hodgson, Peter; Potter, Richard; Hayne, Manus.
2021 5th IEEE Electron Devices Technology & Manufacturing Conference (EDTM). IEEE, 2021. p. 1-3.Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Conference contribution/Paper › peer-review
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TY - GEN
T1 - Demonstration of a Fast, Low-Voltage, III-V Semiconductor, Non-Volatile Memory
AU - Lane, Dominic
AU - Hodgson, Peter
AU - Potter, Richard
AU - Hayne, Manus
PY - 2021/5/12
Y1 - 2021/5/12
N2 - ULTRARAM™ is a III-V semiconductor memory technology which exploits resonant tunneling to allow ultra-low-energy memory logic switching (per unit area), whilst retaining non-volatility. Single-cell memories developed on GaAs substrates with a revised design and atomic-layer-deposition Al 2 O 3 gate dielectric demonstrate significant improvements compared to prior prototypes. Floating-gate (FG) memories with 20-μm gate length show 0/1 state contrast from 2.5-V program-read-erase-read (P/E) cycles with 500-μs pulse duration, which would scale to sub-ns switching speed at 20-nm node. Nonvolatility is confirmed by memory retention tests of 4×10 3 s with both 0 and 1 states completely invariant. Single cells demonstrate promising endurance results, undergoing 10 4 cycles without degradation. P/E cycling and disturbance tests are performed using half-voltages (±1.25 V), validating the high-density random access memory (RAM) architecture proposed previously. Finally, memory logic is retained after an equivalent of >10 5 P/E disturbances.
AB - ULTRARAM™ is a III-V semiconductor memory technology which exploits resonant tunneling to allow ultra-low-energy memory logic switching (per unit area), whilst retaining non-volatility. Single-cell memories developed on GaAs substrates with a revised design and atomic-layer-deposition Al 2 O 3 gate dielectric demonstrate significant improvements compared to prior prototypes. Floating-gate (FG) memories with 20-μm gate length show 0/1 state contrast from 2.5-V program-read-erase-read (P/E) cycles with 500-μs pulse duration, which would scale to sub-ns switching speed at 20-nm node. Nonvolatility is confirmed by memory retention tests of 4×10 3 s with both 0 and 1 states completely invariant. Single cells demonstrate promising endurance results, undergoing 10 4 cycles without degradation. P/E cycling and disturbance tests are performed using half-voltages (±1.25 V), validating the high-density random access memory (RAM) architecture proposed previously. Finally, memory logic is retained after an equivalent of >10 5 P/E disturbances.
U2 - 10.1109/EDTM50988.2021.9420825
DO - 10.1109/EDTM50988.2021.9420825
M3 - Conference contribution/Paper
SN - 9781728181776
SP - 1
EP - 3
BT - 2021 5th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)
PB - IEEE
ER -