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    Rights statement: Copyright © 2011 M. H. Ghadiry et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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Design and analysis of a new carbon nanotube full adder cell

Research output: Contribution to Journal/Magazine › Journal article › peer-review

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Design and analysis of a new carbon nanotube full adder cell. / Ghadiry, M. H.; Manaf, Asrulnizam Abd; Ahmadi, Mohammad Taghi et al.
In: Journal of Nanomaterials, Vol. 2011, 906237, 2011.

Research output: Contribution to Journal/Magazine › Journal article › peer-review

Harvard

Ghadiry, MH, Manaf, AA, Ahmadi, MT, Sadeghi, H & Senejani, MN 2011, 'Design and analysis of a new carbon nanotube full adder cell', Journal of Nanomaterials, vol. 2011, 906237. https://doi.org/10.1155/2011/906237

APA

Ghadiry, M. H., Manaf, A. A., Ahmadi, M. T., Sadeghi, H., & Senejani, M. N. (2011). Design and analysis of a new carbon nanotube full adder cell. Journal of Nanomaterials, 2011, Article 906237. https://doi.org/10.1155/2011/906237

Vancouver

Ghadiry MH, Manaf AA, Ahmadi MT, Sadeghi H, Senejani MN. Design and analysis of a new carbon nanotube full adder cell. Journal of Nanomaterials. 2011;2011:906237. doi: 10.1155/2011/906237

Author

Ghadiry, M. H. ; Manaf, Asrulnizam Abd ; Ahmadi, Mohammad Taghi et al. / Design and analysis of a new carbon nanotube full adder cell. In: Journal of Nanomaterials. 2011 ; Vol. 2011.

Bibtex

@article{b5a469ebc3094ab0a5c2b091a681d945,
title = "Design and analysis of a new carbon nanotube full adder cell",
abstract = "A novel full adder circuit is presented. The main aim is to reduce power delay product (PDP) in the presented full adder cell. A new method is used in order to design a full-swing full adder cell with low number of transistors. The proposed full adder is implemented in MOSFET-like carbon nanotube technology and the layout is provided based on standard 32 nm technology from MOSIS. The simulation results using HSPICE show that there are substantial improvements in both power and performance of the proposed circuit compared to the latest designs. In addition, the proposed circuit has been implemented in conventional 32 nm process to compare the benefits of using MOSFET-like carbon nanotubes in arithmetic circuits over conventional CMOS technology. The proposed circuit can be applied in very high performance and ultra-low-power applications.",
author = "Ghadiry, {M. H.} and Manaf, {Asrulnizam Abd} and Ahmadi, {Mohammad Taghi} and Hatef Sadeghi and Senejani, {M. Nadi}",
note = "Copyright {\textcopyright} 2011 M. H. Ghadiry et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.",
year = "2011",
doi = "10.1155/2011/906237",
language = "English",
volume = "2011",
journal = "Journal of Nanomaterials",
issn = "1687-4110",
publisher = "Hindawi Publishing Corporation",

}

RIS

TY - JOUR

T1 - Design and analysis of a new carbon nanotube full adder cell

AU - Ghadiry, M. H.

AU - Manaf, Asrulnizam Abd

AU - Ahmadi, Mohammad Taghi

AU - Sadeghi, Hatef

AU - Senejani, M. Nadi

N1 - Copyright © 2011 M. H. Ghadiry et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

PY - 2011

Y1 - 2011

N2 - A novel full adder circuit is presented. The main aim is to reduce power delay product (PDP) in the presented full adder cell. A new method is used in order to design a full-swing full adder cell with low number of transistors. The proposed full adder is implemented in MOSFET-like carbon nanotube technology and the layout is provided based on standard 32 nm technology from MOSIS. The simulation results using HSPICE show that there are substantial improvements in both power and performance of the proposed circuit compared to the latest designs. In addition, the proposed circuit has been implemented in conventional 32 nm process to compare the benefits of using MOSFET-like carbon nanotubes in arithmetic circuits over conventional CMOS technology. The proposed circuit can be applied in very high performance and ultra-low-power applications.

AB - A novel full adder circuit is presented. The main aim is to reduce power delay product (PDP) in the presented full adder cell. A new method is used in order to design a full-swing full adder cell with low number of transistors. The proposed full adder is implemented in MOSFET-like carbon nanotube technology and the layout is provided based on standard 32 nm technology from MOSIS. The simulation results using HSPICE show that there are substantial improvements in both power and performance of the proposed circuit compared to the latest designs. In addition, the proposed circuit has been implemented in conventional 32 nm process to compare the benefits of using MOSFET-like carbon nanotubes in arithmetic circuits over conventional CMOS technology. The proposed circuit can be applied in very high performance and ultra-low-power applications.

U2 - 10.1155/2011/906237

DO - 10.1155/2011/906237

M3 - Journal article

VL - 2011

JO - Journal of Nanomaterials

JF - Journal of Nanomaterials

SN - 1687-4110

M1 - 906237

ER -