Home > Research > Publications & Outputs > Design, fabrication and characterisation of a n...

Electronic data

  • 2018TiznoPhD

    Final published version, 503 MB, PDF document

    Available under license: CC BY-ND: Creative Commons Attribution-NoDerivatives 4.0 International License

Text available via DOI:

View graph of relations

Design, fabrication and characterisation of a novel memory device based on III-V semiconductors

Research output: ThesisDoctoral Thesis

Published

Standard

Design, fabrication and characterisation of a novel memory device based on III-V semiconductors. / Tizno, Ofogh.
Lancaster: Lancaster University, 2018. 220 p.

Research output: ThesisDoctoral Thesis

Harvard

APA

Vancouver

Tizno O. Design, fabrication and characterisation of a novel memory device based on III-V semiconductors. Lancaster: Lancaster University, 2018. 220 p. doi: 10.17635/lancaster/thesis/486

Author

Bibtex

@phdthesis{9d10c8f3d4c04c9a8554300dd7a223f0,
title = "Design, fabrication and characterisation of a novel memory device based on III-V semiconductors",
abstract = "This work is a report on the design, fabrication and room-temperature testing of a novel memory device based on III-V compound semiconductor heterostructures. Using the interfacial misfit (IMF) array growth mode, III-V binary (InAs, AlSb, GaSb) and ternary (AlGaSb, AlGaAs) materials were grown on a lattice mismatched GaAs substrate by molecular beam epitaxy (MBE) under optimised growth conditions. Like Flash, the device is a floating-gate memory, with a junctionless channel to allow non-destructive read of the stored charge. However, there are no oxide layers. Instead, InAs/AlSb quantum wells and barriers provide profound electron confinement in the InAs floating gate. Modelling was undertaken to mathematically calculate the room temperature band diagram of the structure at equilibrium and under bias conditions, along with the electron/hole densities and electron energy levels and wave functions. Three sets of devices with slightly different semiconductor layers were designed and successfully fabricated by employing a top-down processing approach. Room temperature electrical measurements showed reliable memory characteristics with promising durability following thousands of non-destructive read operations and hundreds of erase-read-write-read cycles between “0” and “1” memory states. Non-volatile data retention of at least 104 s in combination with switching at ≤ 2.6V was achieved by use of the extraordinary 2.1eV conduction band offsets of InAs/AlSb and a triple-barrier resonant-tunnelling structure, with excellent prospects for high-speed operation and high endurance. The combination of low-voltage operation and small capacitance suggests a switching energy per unitarea 100 and 1000 times smaller than dynamic random access memory (DRAM) and Flash, respectively. These findings hint at the potential of this memory device to be considered as a candidate universal memory.",
author = "Ofogh Tizno",
year = "2018",
doi = "10.17635/lancaster/thesis/486",
language = "English",
publisher = "Lancaster University",
school = "Lancaster University",

}

RIS

TY - BOOK

T1 - Design, fabrication and characterisation of a novel memory device based on III-V semiconductors

AU - Tizno, Ofogh

PY - 2018

Y1 - 2018

N2 - This work is a report on the design, fabrication and room-temperature testing of a novel memory device based on III-V compound semiconductor heterostructures. Using the interfacial misfit (IMF) array growth mode, III-V binary (InAs, AlSb, GaSb) and ternary (AlGaSb, AlGaAs) materials were grown on a lattice mismatched GaAs substrate by molecular beam epitaxy (MBE) under optimised growth conditions. Like Flash, the device is a floating-gate memory, with a junctionless channel to allow non-destructive read of the stored charge. However, there are no oxide layers. Instead, InAs/AlSb quantum wells and barriers provide profound electron confinement in the InAs floating gate. Modelling was undertaken to mathematically calculate the room temperature band diagram of the structure at equilibrium and under bias conditions, along with the electron/hole densities and electron energy levels and wave functions. Three sets of devices with slightly different semiconductor layers were designed and successfully fabricated by employing a top-down processing approach. Room temperature electrical measurements showed reliable memory characteristics with promising durability following thousands of non-destructive read operations and hundreds of erase-read-write-read cycles between “0” and “1” memory states. Non-volatile data retention of at least 104 s in combination with switching at ≤ 2.6V was achieved by use of the extraordinary 2.1eV conduction band offsets of InAs/AlSb and a triple-barrier resonant-tunnelling structure, with excellent prospects for high-speed operation and high endurance. The combination of low-voltage operation and small capacitance suggests a switching energy per unitarea 100 and 1000 times smaller than dynamic random access memory (DRAM) and Flash, respectively. These findings hint at the potential of this memory device to be considered as a candidate universal memory.

AB - This work is a report on the design, fabrication and room-temperature testing of a novel memory device based on III-V compound semiconductor heterostructures. Using the interfacial misfit (IMF) array growth mode, III-V binary (InAs, AlSb, GaSb) and ternary (AlGaSb, AlGaAs) materials were grown on a lattice mismatched GaAs substrate by molecular beam epitaxy (MBE) under optimised growth conditions. Like Flash, the device is a floating-gate memory, with a junctionless channel to allow non-destructive read of the stored charge. However, there are no oxide layers. Instead, InAs/AlSb quantum wells and barriers provide profound electron confinement in the InAs floating gate. Modelling was undertaken to mathematically calculate the room temperature band diagram of the structure at equilibrium and under bias conditions, along with the electron/hole densities and electron energy levels and wave functions. Three sets of devices with slightly different semiconductor layers were designed and successfully fabricated by employing a top-down processing approach. Room temperature electrical measurements showed reliable memory characteristics with promising durability following thousands of non-destructive read operations and hundreds of erase-read-write-read cycles between “0” and “1” memory states. Non-volatile data retention of at least 104 s in combination with switching at ≤ 2.6V was achieved by use of the extraordinary 2.1eV conduction band offsets of InAs/AlSb and a triple-barrier resonant-tunnelling structure, with excellent prospects for high-speed operation and high endurance. The combination of low-voltage operation and small capacitance suggests a switching energy per unitarea 100 and 1000 times smaller than dynamic random access memory (DRAM) and Flash, respectively. These findings hint at the potential of this memory device to be considered as a candidate universal memory.

U2 - 10.17635/lancaster/thesis/486

DO - 10.17635/lancaster/thesis/486

M3 - Doctoral Thesis

PB - Lancaster University

CY - Lancaster

ER -