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Designing high-performance & reliable superscalar architectures the out of order reliable superscalar (O3RS) approach

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Designing high-performance & reliable superscalar architectures the out of order reliable superscalar (O3RS) approach. / Mendelson, A.; Suri, Neeraj.
Proceeding International Conference on Dependable Systems and Networks. IEEE, 2000. p. 473-481.

Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSNConference contribution/Paperpeer-review

Harvard

Mendelson, A & Suri, N 2000, Designing high-performance & reliable superscalar architectures the out of order reliable superscalar (O3RS) approach. in Proceeding International Conference on Dependable Systems and Networks. IEEE, pp. 473-481, International Conference on Dependable Systems and Networks. , New York, New York, United States, 25/06/00. https://doi.org/10.1109/ICDSN.2000.857578

APA

Mendelson, A., & Suri, N. (2000). Designing high-performance & reliable superscalar architectures the out of order reliable superscalar (O3RS) approach. In Proceeding International Conference on Dependable Systems and Networks (pp. 473-481). IEEE. https://doi.org/10.1109/ICDSN.2000.857578

Vancouver

Mendelson A, Suri N. Designing high-performance & reliable superscalar architectures the out of order reliable superscalar (O3RS) approach. In Proceeding International Conference on Dependable Systems and Networks. IEEE. 2000. p. 473-481 doi: 10.1109/ICDSN.2000.857578

Author

Mendelson, A. ; Suri, Neeraj. / Designing high-performance & reliable superscalar architectures the out of order reliable superscalar (O3RS) approach. Proceeding International Conference on Dependable Systems and Networks. IEEE, 2000. pp. 473-481

Bibtex

@inproceedings{2768f01e3fd2497b83278cd3df82e493,
title = "Designing high-performance & reliable superscalar architectures the out of order reliable superscalar (O3RS) approach",
abstract = "As VLSI geometry continues to shrink and the level of integration increases, it is expected that the probability of faults, particularly transient faults, will increase in future microprocessors. So far, fault tolerance has chiefly been considered for special purpose or safety critical systems, but future technology will likely require integrating fault tolerance techniques into commercial systems. Such systems require low cost solutions that are transparent to the system operation and do not degrade overall performance. This paper introduces a new superscalar architecture, termed as 03RS that aims to incorporate such simple fault tolerance mechanisms as part of the basic architecture.",
keywords = "Pipelines, Superscalar architectures, Transient errors/recovery, Out of Order Reliable Superscalar approach, Transient faults, Computer system recovery, Design, Error correction, Fault tolerant computer systems, Pipeline processing systems, Systems analysis, Technological forecasting, Computer architecture",
author = "A. Mendelson and Neeraj Suri",
year = "2000",
month = jun,
day = "25",
doi = "10.1109/ICDSN.2000.857578",
language = "English",
isbn = "0769507077",
pages = "473--481",
booktitle = "Proceeding International Conference on Dependable Systems and Networks",
publisher = "IEEE",
note = "International Conference on Dependable Systems and Networks. , DSN 2000 ; Conference date: 25-06-2000 Through 28-06-2000",

}

RIS

TY - GEN

T1 - Designing high-performance & reliable superscalar architectures the out of order reliable superscalar (O3RS) approach

AU - Mendelson, A.

AU - Suri, Neeraj

PY - 2000/6/25

Y1 - 2000/6/25

N2 - As VLSI geometry continues to shrink and the level of integration increases, it is expected that the probability of faults, particularly transient faults, will increase in future microprocessors. So far, fault tolerance has chiefly been considered for special purpose or safety critical systems, but future technology will likely require integrating fault tolerance techniques into commercial systems. Such systems require low cost solutions that are transparent to the system operation and do not degrade overall performance. This paper introduces a new superscalar architecture, termed as 03RS that aims to incorporate such simple fault tolerance mechanisms as part of the basic architecture.

AB - As VLSI geometry continues to shrink and the level of integration increases, it is expected that the probability of faults, particularly transient faults, will increase in future microprocessors. So far, fault tolerance has chiefly been considered for special purpose or safety critical systems, but future technology will likely require integrating fault tolerance techniques into commercial systems. Such systems require low cost solutions that are transparent to the system operation and do not degrade overall performance. This paper introduces a new superscalar architecture, termed as 03RS that aims to incorporate such simple fault tolerance mechanisms as part of the basic architecture.

KW - Pipelines

KW - Superscalar architectures

KW - Transient errors/recovery

KW - Out of Order Reliable Superscalar approach

KW - Transient faults

KW - Computer system recovery

KW - Design

KW - Error correction

KW - Fault tolerant computer systems

KW - Pipeline processing systems

KW - Systems analysis

KW - Technological forecasting

KW - Computer architecture

U2 - 10.1109/ICDSN.2000.857578

DO - 10.1109/ICDSN.2000.857578

M3 - Conference contribution/Paper

SN - 0769507077

SP - 473

EP - 481

BT - Proceeding International Conference on Dependable Systems and Networks

PB - IEEE

T2 - International Conference on Dependable Systems and Networks.

Y2 - 25 June 2000 through 28 June 2000

ER -