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Early selection of system implementation choice among SoC, SoP and 3-D integration.

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Early selection of system implementation choice among SoC, SoP and 3-D integration. / Weerasekera, Roshan; Zheng, Li-Rong; Pamunuwa, Dinesh B. et al.
Proc. International System-On-Chip Conference (SOCC). Hsin Chu, Taiwan: IEEE, 2007.

Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

Harvard

Weerasekera, R, Zheng, L-R, Pamunuwa, DB & Tenhunen, H 2007, Early selection of system implementation choice among SoC, SoP and 3-D integration. in Proc. International System-On-Chip Conference (SOCC). IEEE, Hsin Chu, Taiwan. https://doi.org/10.1109/SOCC.2007.4545455

APA

Weerasekera, R., Zheng, L.-R., Pamunuwa, D. B., & Tenhunen, H. (2007). Early selection of system implementation choice among SoC, SoP and 3-D integration. In Proc. International System-On-Chip Conference (SOCC) IEEE. https://doi.org/10.1109/SOCC.2007.4545455

Vancouver

Weerasekera R, Zheng LR, Pamunuwa DB, Tenhunen H. Early selection of system implementation choice among SoC, SoP and 3-D integration. In Proc. International System-On-Chip Conference (SOCC). Hsin Chu, Taiwan: IEEE. 2007 doi: 10.1109/SOCC.2007.4545455

Author

Weerasekera, Roshan ; Zheng, Li-Rong ; Pamunuwa, Dinesh B. et al. / Early selection of system implementation choice among SoC, SoP and 3-D integration. Proc. International System-On-Chip Conference (SOCC). Hsin Chu, Taiwan : IEEE, 2007.

Bibtex

@inbook{b37c422055d244218b48cdb942328d07,
title = "Early selection of system implementation choice among SoC, SoP and 3-D integration.",
abstract = "Recently there is a tendency for shifting the planar SoC single-chip solutions to different alternative options as tiled silicon and single-level embedded modules as well as 3-D integration, and the designers confronted with several system design options. To get a true improvement in performance, a very careful analysis using detailed models at different hierarchical levels is crucial. In this work, we present a cohesive analysis of the technological, cost and performance trade-offs for implementing digital and mixed-mode systems considering the choices between 2-D and 3-D integration and their ramifications.",
author = "Roshan Weerasekera and Li-Rong Zheng and Pamunuwa, {Dinesh B.} and Hannu Tenhunen",
note = "{"}{\textcopyright}2007 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.{"} {"}This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.{"}",
year = "2007",
month = sep,
doi = "10.1109/SOCC.2007.4545455",
language = "English",
isbn = "978-1-4244-1592-2",
booktitle = "Proc. International System-On-Chip Conference (SOCC)",
publisher = "IEEE",

}

RIS

TY - CHAP

T1 - Early selection of system implementation choice among SoC, SoP and 3-D integration.

AU - Weerasekera, Roshan

AU - Zheng, Li-Rong

AU - Pamunuwa, Dinesh B.

AU - Tenhunen, Hannu

N1 - "©2007 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE." "This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder."

PY - 2007/9

Y1 - 2007/9

N2 - Recently there is a tendency for shifting the planar SoC single-chip solutions to different alternative options as tiled silicon and single-level embedded modules as well as 3-D integration, and the designers confronted with several system design options. To get a true improvement in performance, a very careful analysis using detailed models at different hierarchical levels is crucial. In this work, we present a cohesive analysis of the technological, cost and performance trade-offs for implementing digital and mixed-mode systems considering the choices between 2-D and 3-D integration and their ramifications.

AB - Recently there is a tendency for shifting the planar SoC single-chip solutions to different alternative options as tiled silicon and single-level embedded modules as well as 3-D integration, and the designers confronted with several system design options. To get a true improvement in performance, a very careful analysis using detailed models at different hierarchical levels is crucial. In this work, we present a cohesive analysis of the technological, cost and performance trade-offs for implementing digital and mixed-mode systems considering the choices between 2-D and 3-D integration and their ramifications.

U2 - 10.1109/SOCC.2007.4545455

DO - 10.1109/SOCC.2007.4545455

M3 - Chapter

SN - 978-1-4244-1592-2

BT - Proc. International System-On-Chip Conference (SOCC)

PB - IEEE

CY - Hsin Chu, Taiwan

ER -