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Enhancing FPGA robustness via generic monitoring IP cores

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  • A. Biedermann
  • T. Piper
  • L. Patzina
  • S. Patzina
  • S.A. Huss
  • A. Schürr
  • Neeraj Suri
Publication date2011
Host publicationProceedings of the 1st International Conference on Pervasive and Embedded Computing and Communication Systems - Volume 1: PECCS, 2011, Vilamoura, Algarve, Portugal
Number of pages8
ISBN (Print)9789898425485
<mark>Original language</mark>English


Today, state of the art technology allows a very dense integration of embedded HW/SW designs. As a consequence, more errors are introduced in these circuits that have to be observed during run-time. Adding monitors to a design enables the recognition of and the reaction to these threats, but, usually, monitors have to be developed for every individual FPGA design. Our approach provides generic IP cores that permit the monitoring of arbitrary hardware modules. Furthermore, by providing a central monitoring module, statements about the behaviour of the entire system can be made.