Standard
Enhancing FPGA robustness via generic monitoring IP cores. / Biedermann, A.; Piper, T.; Patzina, L. et al.
Proceedings of the 1st International Conference on Pervasive and Embedded Computing and Communication Systems - Volume 1: PECCS, 2011, Vilamoura, Algarve, Portugal. SciTePress, 2011. p. 379-386.
Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Conference contribution/Paper › peer-review
Harvard
Biedermann, A, Piper, T, Patzina, L, Patzina, S, Huss, SA, Schürr, A
& Suri, N 2011,
Enhancing FPGA robustness via generic monitoring IP cores. in
Proceedings of the 1st International Conference on Pervasive and Embedded Computing and Communication Systems - Volume 1: PECCS, 2011, Vilamoura, Algarve, Portugal. SciTePress, pp. 379-386.
https://doi.org/10.5220/0003353503790386APA
Biedermann, A., Piper, T., Patzina, L., Patzina, S., Huss, S. A., Schürr, A.
, & Suri, N. (2011).
Enhancing FPGA robustness via generic monitoring IP cores. In
Proceedings of the 1st International Conference on Pervasive and Embedded Computing and Communication Systems - Volume 1: PECCS, 2011, Vilamoura, Algarve, Portugal (pp. 379-386). SciTePress.
https://doi.org/10.5220/0003353503790386Vancouver
Biedermann A, Piper T, Patzina L, Patzina S, Huss SA, Schürr A et al.
Enhancing FPGA robustness via generic monitoring IP cores. In Proceedings of the 1st International Conference on Pervasive and Embedded Computing and Communication Systems - Volume 1: PECCS, 2011, Vilamoura, Algarve, Portugal. SciTePress. 2011. p. 379-386 doi: 10.5220/0003353503790386
Author
Biedermann, A. ; Piper, T. ; Patzina, L. et al. /
Enhancing FPGA robustness via generic monitoring IP cores. Proceedings of the 1st International Conference on Pervasive and Embedded Computing and Communication Systems - Volume 1: PECCS, 2011, Vilamoura, Algarve, Portugal. SciTePress, 2011. pp. 379-386
Bibtex
@inproceedings{09aee390163c440e8dfc7923630abfc0,
title = "Enhancing FPGA robustness via generic monitoring IP cores",
abstract = "Today, state of the art technology allows a very dense integration of embedded HW/SW designs. As a consequence, more errors are introduced in these circuits that have to be observed during run-time. Adding monitors to a design enables the recognition of and the reaction to these threats, but, usually, monitors have to be developed for every individual FPGA design. Our approach provides generic IP cores that permit the monitoring of arbitrary hardware modules. Furthermore, by providing a central monitoring module, statements about the behaviour of the entire system can be made.",
keywords = "Embedded HW/SW design, FPGA monitoring, System monitoring, Dense integration, Entire system, FPGA design, Hardware modules, IP core, Runtimes, State-of-the-art technology, Arts computing, Communication systems, Design, Embedded software, Embedded systems",
author = "A. Biedermann and T. Piper and L. Patzina and S. Patzina and S.A. Huss and A. Sch{\"u}rr and Neeraj Suri",
year = "2011",
doi = "10.5220/0003353503790386",
language = "English",
isbn = "9789898425485",
pages = "379--386",
booktitle = "Proceedings of the 1st International Conference on Pervasive and Embedded Computing and Communication Systems - Volume 1",
publisher = "SciTePress",
}
RIS
TY - GEN
T1 - Enhancing FPGA robustness via generic monitoring IP cores
AU - Biedermann, A.
AU - Piper, T.
AU - Patzina, L.
AU - Patzina, S.
AU - Huss, S.A.
AU - Schürr, A.
AU - Suri, Neeraj
PY - 2011
Y1 - 2011
N2 - Today, state of the art technology allows a very dense integration of embedded HW/SW designs. As a consequence, more errors are introduced in these circuits that have to be observed during run-time. Adding monitors to a design enables the recognition of and the reaction to these threats, but, usually, monitors have to be developed for every individual FPGA design. Our approach provides generic IP cores that permit the monitoring of arbitrary hardware modules. Furthermore, by providing a central monitoring module, statements about the behaviour of the entire system can be made.
AB - Today, state of the art technology allows a very dense integration of embedded HW/SW designs. As a consequence, more errors are introduced in these circuits that have to be observed during run-time. Adding monitors to a design enables the recognition of and the reaction to these threats, but, usually, monitors have to be developed for every individual FPGA design. Our approach provides generic IP cores that permit the monitoring of arbitrary hardware modules. Furthermore, by providing a central monitoring module, statements about the behaviour of the entire system can be made.
KW - Embedded HW/SW design
KW - FPGA monitoring
KW - System monitoring
KW - Dense integration
KW - Entire system
KW - FPGA design
KW - Hardware modules
KW - IP core
KW - Runtimes
KW - State-of-the-art technology
KW - Arts computing
KW - Communication systems
KW - Design
KW - Embedded software
KW - Embedded systems
U2 - 10.5220/0003353503790386
DO - 10.5220/0003353503790386
M3 - Conference contribution/Paper
SN - 9789898425485
SP - 379
EP - 386
BT - Proceedings of the 1st International Conference on Pervasive and Embedded Computing and Communication Systems - Volume 1
PB - SciTePress
ER -
