There is provided a memory cell for storing one or more bits of information. The memory cell comprises a semiconductor substrate on which is provided a source terminal, a drain terminal and a channel extending between the source and drain terminals. The memory cell further comprises a control gate and a floating gate, the floating gate being disposed between the control gate and the channel, and the floating gate being electrically isolated from the control gate and the channel by charge barriers and being configured to enable the selective passage of charge carriers into and out of the floating gate, in write and erase operations, to provide at least first and second occupancy states of the floating gate. The channel is arranged to provide a minimum threshold voltage to be applied between the control gate and the substrate for introducing charge carriers into the channel from the substrate to make the channel conductive, the minimum threshold voltage being dependent on the occupancy state of the floating gate, such that a read voltage may be applied between the control gate and the substrate that will provide a conductive channel for a first occupancy state of the floating gate and a non-conductive channel for a second occupancy state of the floating gate.