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Inhibiting the current spikes within the channel layer of LiCoO2-based three-terminal synaptic transistors

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Inhibiting the current spikes within the channel layer of LiCoO2-based three-terminal synaptic transistors. / Chen, Yue; Zhang, Weijian; Lu, Yuezhen et al.
In: Applied Physics Reviews, Vol. 11, No. 4, 041407, 01.12.2024.

Research output: Contribution to Journal/Magazine › Journal article › peer-review

Harvard

Chen, Y, Zhang, W, Lu, Y, Chen, M, Chen, J, Lu, H, Niu, Y, Zhao, G, Tao, J, Li, J, Lin, Y, Kolosov, O & Huang, Z 2024, 'Inhibiting the current spikes within the channel layer of LiCoO2-based three-terminal synaptic transistors', Applied Physics Reviews, vol. 11, no. 4, 041407. https://doi.org/10.1063/5.0200811

APA

Chen, Y., Zhang, W., Lu, Y., Chen, M., Chen, J., Lu, H., Niu, Y., Zhao, G., Tao, J., Li, J., Lin, Y., Kolosov, O., & Huang, Z. (2024). Inhibiting the current spikes within the channel layer of LiCoO2-based three-terminal synaptic transistors. Applied Physics Reviews, 11(4), Article 041407. https://doi.org/10.1063/5.0200811

Vancouver

Chen Y, Zhang W, Lu Y, Chen M, Chen J, Lu H et al. Inhibiting the current spikes within the channel layer of LiCoO2-based three-terminal synaptic transistors. Applied Physics Reviews. 2024 Dec 1;11(4):041407. Epub 2024 Oct 9. doi: 10.1063/5.0200811

Author

Chen, Yue ; Zhang, Weijian ; Lu, Yuezhen et al. / Inhibiting the current spikes within the channel layer of LiCoO2-based three-terminal synaptic transistors. In: Applied Physics Reviews. 2024 ; Vol. 11, No. 4.

Bibtex

@article{3c2795c0a74749e3bbc4f9e5fc2da8d8,
title = "Inhibiting the current spikes within the channel layer of LiCoO2-based three-terminal synaptic transistors",
abstract = "Synaptic transistors, which emulate the behavior of biological synapses, play a vital role in information processing and storage in neuromorphic systems. However, the occurrence of excessive current spikes during the updating of synaptic weight poses challenges to the stability, accuracy, and power consumption of synaptic transistors. In this work, we experimentally investigate the main factors for the generation of current spikes in the three-terminal synaptic transistors that use LiCoO2 (LCO), a mixed ionic-electronic conductor, as the channel layer. Kelvin probe force microscopy and impedance testing results reveal that ion migration and adsorption at the drain–source-channel interface cause the current spikes that compromise the device's performance. By controlling the crystal orientation of the LCO channel layer to impede the in-plane migration of lithium ions, we show that the LCO channel layer with the (104) preferred orientation can effectively suppress both the peak current and power consumption in the synaptic transistors. Our study provides a unique insight into controlling the crystallographic orientation for the design of high-speed, high-robustness, and low-power consumption nano-memristor devices.",
author = "Yue Chen and Weijian Zhang and Yuezhen Lu and Minzhen Chen and Jing Chen and Hongyi Lu and Yubiao Niu and Guiying Zhao and Jianming Tao and Jiaxin Li and Yingbin Lin and Oleg Kolosov and Zhigao Huang",
year = "2024",
month = dec,
day = "1",
doi = "10.1063/5.0200811",
language = "English",
volume = "11",
journal = "Applied Physics Reviews",
issn = "1931-9401",
publisher = "American Institute of Physics Publising LLC",
number = "4",

}

RIS

TY - JOUR

T1 - Inhibiting the current spikes within the channel layer of LiCoO2-based three-terminal synaptic transistors

AU - Chen, Yue

AU - Zhang, Weijian

AU - Lu, Yuezhen

AU - Chen, Minzhen

AU - Chen, Jing

AU - Lu, Hongyi

AU - Niu, Yubiao

AU - Zhao, Guiying

AU - Tao, Jianming

AU - Li, Jiaxin

AU - Lin, Yingbin

AU - Kolosov, Oleg

AU - Huang, Zhigao

PY - 2024/12/1

Y1 - 2024/12/1

N2 - Synaptic transistors, which emulate the behavior of biological synapses, play a vital role in information processing and storage in neuromorphic systems. However, the occurrence of excessive current spikes during the updating of synaptic weight poses challenges to the stability, accuracy, and power consumption of synaptic transistors. In this work, we experimentally investigate the main factors for the generation of current spikes in the three-terminal synaptic transistors that use LiCoO2 (LCO), a mixed ionic-electronic conductor, as the channel layer. Kelvin probe force microscopy and impedance testing results reveal that ion migration and adsorption at the drain–source-channel interface cause the current spikes that compromise the device's performance. By controlling the crystal orientation of the LCO channel layer to impede the in-plane migration of lithium ions, we show that the LCO channel layer with the (104) preferred orientation can effectively suppress both the peak current and power consumption in the synaptic transistors. Our study provides a unique insight into controlling the crystallographic orientation for the design of high-speed, high-robustness, and low-power consumption nano-memristor devices.

AB - Synaptic transistors, which emulate the behavior of biological synapses, play a vital role in information processing and storage in neuromorphic systems. However, the occurrence of excessive current spikes during the updating of synaptic weight poses challenges to the stability, accuracy, and power consumption of synaptic transistors. In this work, we experimentally investigate the main factors for the generation of current spikes in the three-terminal synaptic transistors that use LiCoO2 (LCO), a mixed ionic-electronic conductor, as the channel layer. Kelvin probe force microscopy and impedance testing results reveal that ion migration and adsorption at the drain–source-channel interface cause the current spikes that compromise the device's performance. By controlling the crystal orientation of the LCO channel layer to impede the in-plane migration of lithium ions, we show that the LCO channel layer with the (104) preferred orientation can effectively suppress both the peak current and power consumption in the synaptic transistors. Our study provides a unique insight into controlling the crystallographic orientation for the design of high-speed, high-robustness, and low-power consumption nano-memristor devices.

U2 - 10.1063/5.0200811

DO - 10.1063/5.0200811

M3 - Journal article

VL - 11

JO - Applied Physics Reviews

JF - Applied Physics Reviews

SN - 1931-9401

IS - 4

M1 - 041407

ER -