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On signalling over through-silicon via (TSV) interconnects in 3-D integrated circuits.

Research output: Contribution to conference - Without ISBN/ISSN › Conference paper › peer-review

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On signalling over through-silicon via (TSV) interconnects in 3-D integrated circuits. / Weerasekera, Roshan; Grange, M.; Pamunuwa, Dinesh B. et al.
2010. 1325-1328 Paper presented at Design Automation and Test in Europe (DATE) Conference, Dresden, Germany.

Research output: Contribution to conference - Without ISBN/ISSN › Conference paper › peer-review

Harvard

Weerasekera, R, Grange, M, Pamunuwa, DB & Tenhunen, H 2010, 'On signalling over through-silicon via (TSV) interconnects in 3-D integrated circuits.', Paper presented at Design Automation and Test in Europe (DATE) Conference, Dresden, Germany, 1/01/10 pp. 1325-1328. <http://www.date-conference.com/proceedings/PAPERS/2010/YEAR.HTM>

APA

Weerasekera, R., Grange, M., Pamunuwa, D. B., & Tenhunen, H. (2010). On signalling over through-silicon via (TSV) interconnects in 3-D integrated circuits.. 1325-1328. Paper presented at Design Automation and Test in Europe (DATE) Conference, Dresden, Germany. http://www.date-conference.com/proceedings/PAPERS/2010/YEAR.HTM

Vancouver

Weerasekera R, Grange M, Pamunuwa DB, Tenhunen H. On signalling over through-silicon via (TSV) interconnects in 3-D integrated circuits.. 2010. Paper presented at Design Automation and Test in Europe (DATE) Conference, Dresden, Germany.

Author

Weerasekera, Roshan ; Grange, M. ; Pamunuwa, Dinesh B. et al. / On signalling over through-silicon via (TSV) interconnects in 3-D integrated circuits. Paper presented at Design Automation and Test in Europe (DATE) Conference, Dresden, Germany.4 p.

Bibtex

@conference{29f3ad9da36b42aba967d2fcf56d9d85,
title = "On signalling over through-silicon via (TSV) interconnects in 3-D integrated circuits.",
abstract = "This paper discusses signal integrity (SI) issues and signalling techniques for Through Silicon Via (TSV) interconnects in 3-D Integrated Circuits (ICs). Field-solver extracted parasitics of TSVs have been employed in Spice simulations to investigate the effect of each parasitic component on performance metrics such as delay and crosstalk and identify a reduced-order electrical model that captures all relevant effects. We show that in dense TSV structures voltage-mode (VM) signalling does not lend itself to achieving high data-rates, and that current-mode (CM) signalling is more effective for high throughput signalling as well as jitter reduction. Data rates, energy consumption and coupled noise for the different signalling modes are extracted.",
author = "Roshan Weerasekera and M. Grange and Pamunuwa, {Dinesh B.} and Hannu Tenhunen",
year = "2010",
month = mar,
language = "English",
pages = "1325--1328",
note = "Design Automation and Test in Europe (DATE) Conference ; Conference date: 01-01-2010",

}

RIS

TY - CONF

T1 - On signalling over through-silicon via (TSV) interconnects in 3-D integrated circuits.

AU - Weerasekera, Roshan

AU - Grange, M.

AU - Pamunuwa, Dinesh B.

AU - Tenhunen, Hannu

PY - 2010/3

Y1 - 2010/3

N2 - This paper discusses signal integrity (SI) issues and signalling techniques for Through Silicon Via (TSV) interconnects in 3-D Integrated Circuits (ICs). Field-solver extracted parasitics of TSVs have been employed in Spice simulations to investigate the effect of each parasitic component on performance metrics such as delay and crosstalk and identify a reduced-order electrical model that captures all relevant effects. We show that in dense TSV structures voltage-mode (VM) signalling does not lend itself to achieving high data-rates, and that current-mode (CM) signalling is more effective for high throughput signalling as well as jitter reduction. Data rates, energy consumption and coupled noise for the different signalling modes are extracted.

AB - This paper discusses signal integrity (SI) issues and signalling techniques for Through Silicon Via (TSV) interconnects in 3-D Integrated Circuits (ICs). Field-solver extracted parasitics of TSVs have been employed in Spice simulations to investigate the effect of each parasitic component on performance metrics such as delay and crosstalk and identify a reduced-order electrical model that captures all relevant effects. We show that in dense TSV structures voltage-mode (VM) signalling does not lend itself to achieving high data-rates, and that current-mode (CM) signalling is more effective for high throughput signalling as well as jitter reduction. Data rates, energy consumption and coupled noise for the different signalling modes are extracted.

M3 - Conference paper

SP - 1325

EP - 1328

T2 - Design Automation and Test in Europe (DATE) Conference

Y2 - 1 January 2010

ER -