Home > Research > Publications & Outputs > Optimising bandwidth over deep sub-micron inter...

Research

Electronic data

Links

Text available via DOI:

View graph of relations

Optimising bandwidth over deep sub-micron interconnect.

Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

Published

Standard

Optimising bandwidth over deep sub-micron interconnect. / Pamunuwa, Dinesh B.; Zheng, Li-Rong; Tenhunen, Hannu.
2002 IEEE International Symposium on Circuits and Systems. Vol. 4 IEEE, 2002. p. IV-193.

Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

Harvard

Pamunuwa, DB, Zheng, L-R & Tenhunen, H 2002, Optimising bandwidth over deep sub-micron interconnect. in 2002 IEEE International Symposium on Circuits and Systems. vol. 4, IEEE, pp. IV-193. https://doi.org/10.1109/ISCAS.2002.1010422

APA

Pamunuwa, D. B., Zheng, L.-R., & Tenhunen, H. (2002). Optimising bandwidth over deep sub-micron interconnect. In 2002 IEEE International Symposium on Circuits and Systems (Vol. 4, pp. IV-193). IEEE. https://doi.org/10.1109/ISCAS.2002.1010422

Vancouver

Pamunuwa DB, Zheng LR, Tenhunen H. Optimising bandwidth over deep sub-micron interconnect. In 2002 IEEE International Symposium on Circuits and Systems. Vol. 4. IEEE. 2002. p. IV-193 doi: 10.1109/ISCAS.2002.1010422

Author

Pamunuwa, Dinesh B. ; Zheng, Li-Rong ; Tenhunen, Hannu. / Optimising bandwidth over deep sub-micron interconnect. 2002 IEEE International Symposium on Circuits and Systems. Vol. 4 IEEE, 2002. pp. IV-193

Bibtex

@inbook{ab42b487e81342708eb9a64dd869aa4a,
title = "Optimising bandwidth over deep sub-micron interconnect.",
abstract = "In deep sub-micron (DSM) circuits proper analysis of interconnect delay is very important. When relatively long wires are placed in parallel, it is essential to include the effects of cross-talk on delay. In a parallel wire structure, the exact spacing and size of the wires determine both the resistance and the distribution of the capacitance between the ground plane and the adjacent signal carrying conductors, and have a direct effect on the delay. Repeater insertion depending on whether it is optimal or constrained, affects the delay in different ways. Considering all these effects we show that there is a clear optimum configuration for the wires which maximises the total bandwidth. Our analysis is valid for lossy interconnects as are typical of wires in DSM technologies.",
author = "Pamunuwa, {Dinesh B.} and Li-Rong Zheng and Hannu Tenhunen",
note = "{"}{\textcopyright}2002 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.{"} {"}This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.{"}",
year = "2002",
doi = "10.1109/ISCAS.2002.1010422",
language = "English",
isbn = "0-7803-7448-7",
volume = "4",
pages = "IV--193",
booktitle = "2002 IEEE International Symposium on Circuits and Systems",
publisher = "IEEE",

}

RIS

TY - CHAP

T1 - Optimising bandwidth over deep sub-micron interconnect.

AU - Pamunuwa, Dinesh B.

AU - Zheng, Li-Rong

AU - Tenhunen, Hannu

N1 - "©2002 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE." "This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder."

PY - 2002

Y1 - 2002

N2 - In deep sub-micron (DSM) circuits proper analysis of interconnect delay is very important. When relatively long wires are placed in parallel, it is essential to include the effects of cross-talk on delay. In a parallel wire structure, the exact spacing and size of the wires determine both the resistance and the distribution of the capacitance between the ground plane and the adjacent signal carrying conductors, and have a direct effect on the delay. Repeater insertion depending on whether it is optimal or constrained, affects the delay in different ways. Considering all these effects we show that there is a clear optimum configuration for the wires which maximises the total bandwidth. Our analysis is valid for lossy interconnects as are typical of wires in DSM technologies.

AB - In deep sub-micron (DSM) circuits proper analysis of interconnect delay is very important. When relatively long wires are placed in parallel, it is essential to include the effects of cross-talk on delay. In a parallel wire structure, the exact spacing and size of the wires determine both the resistance and the distribution of the capacitance between the ground plane and the adjacent signal carrying conductors, and have a direct effect on the delay. Repeater insertion depending on whether it is optimal or constrained, affects the delay in different ways. Considering all these effects we show that there is a clear optimum configuration for the wires which maximises the total bandwidth. Our analysis is valid for lossy interconnects as are typical of wires in DSM technologies.

U2 - 10.1109/ISCAS.2002.1010422

DO - 10.1109/ISCAS.2002.1010422

M3 - Chapter

SN - 0-7803-7448-7

VL - 4

SP - IV-193

BT - 2002 IEEE International Symposium on Circuits and Systems

PB - IEEE

ER -