TY - JOUR

T1 - Pattern-generation and pattern-transfer for single-digit nano devices

AU - Rangelow, Ivo W.

AU - Ahmad, Ahmad

AU - Ivanov, Tzvetan

AU - Kaestner, Marcus

AU - Krivoshapkina, Yana

AU - Angelov, Tihomir

AU - Lenk, Steve

AU - Lenk, Claudia

AU - Ishchuk, Valentyn

AU - Hofmann, Martin

AU - Nechepurenko, Diana

AU - Atanasov, Ivaylo

AU - Volland, Burkhard

AU - Guliyev, Elshad

AU - Durrani, Zahid A. K.

AU - Jones, Mervyn E.

AU - Wang, Chen

AU - Liu, Dixi

AU - Reum, Alexander

AU - Holz, Mathias

AU - Nikolov, Nikolay

AU - Majstrzyk, Wojciech

AU - Gotszalk, Teodor

AU - Staaks, Daniel

AU - Dallorto, Stefano

AU - Olynick, Deirdre L.

PY - 2016/11/3

Y1 - 2016/11/3

N2 - Single-electron devices operating at room temperature require sub-5 nm quantum dots having tunnel junctions of comparable dimensions. Further development in nanoelectronics depends on the capability to generate mesoscopic structures and interfacing these with complementary metal–oxide–semiconductor devices in a single system. The authors employ a combination of two novel methods of fabricating room temperature silicon single-electron transistors (SETs), Fowler–Nordheim scanning probe lithography (F-N SPL) with active cantilevers and cryogenic reactive ion etching followed by pattern-dependent oxidation. The F-N SPL employs a low energy electron exposure of 5–10 nm thick high-resolution molecular resist (Calixarene) resulting in single nanodigit lithographic performance [Rangelow et al., Proc. SPIE 7637, 76370V (2010)]. The followed step of pattern transfer into silicon becomes very challenging because of the extremely low resist thickness, which limits the etching depth. The authors developed a computer simulation code to simulate the reactive ion etching at cryogenic temperatures (−120 °C). In this article, the authors present the alliance of all these technologies used for the manufacturing of SETs capable to operate at room temperatures.

AB - Single-electron devices operating at room temperature require sub-5 nm quantum dots having tunnel junctions of comparable dimensions. Further development in nanoelectronics depends on the capability to generate mesoscopic structures and interfacing these with complementary metal–oxide–semiconductor devices in a single system. The authors employ a combination of two novel methods of fabricating room temperature silicon single-electron transistors (SETs), Fowler–Nordheim scanning probe lithography (F-N SPL) with active cantilevers and cryogenic reactive ion etching followed by pattern-dependent oxidation. The F-N SPL employs a low energy electron exposure of 5–10 nm thick high-resolution molecular resist (Calixarene) resulting in single nanodigit lithographic performance [Rangelow et al., Proc. SPIE 7637, 76370V (2010)]. The followed step of pattern transfer into silicon becomes very challenging because of the extremely low resist thickness, which limits the etching depth. The authors developed a computer simulation code to simulate the reactive ion etching at cryogenic temperatures (−120 °C). In this article, the authors present the alliance of all these technologies used for the manufacturing of SETs capable to operate at room temperatures.

U2 - 10.1116/1.4966556

DO - 10.1116/1.4966556

M3 - Journal article

VL - 34

JO - Journal of Vacuum Science and Technology B

JF - Journal of Vacuum Science and Technology B

SN - 1071-1023

IS - 6

M1 - 06K202

ER -