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Physical Mapping and Performance Study of a Multi-Clock 3-Dimensional Network-on-Chip Mesh.

Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

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Physical Mapping and Performance Study of a Multi-Clock 3-Dimensional Network-on-Chip Mesh. / Grange, M.; Weldezion, A. Y.; Pamunuwa, Dinesh Bandara et al.
Proceedings of the IEEE International Conference on 3D System Integration (3D IC), 2009. San Francisco: IEEE, 2009.

Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

Harvard

Grange, M, Weldezion, AY, Pamunuwa, DB, Weerasekera, R, Zhonghai, L, Jantsch, A & Shippen, D 2009, Physical Mapping and Performance Study of a Multi-Clock 3-Dimensional Network-on-Chip Mesh. in Proceedings of the IEEE International Conference on 3D System Integration (3D IC), 2009. IEEE, San Francisco. https://doi.org/10.1109/3DIC.2009.5306540

APA

Grange, M., Weldezion, A. Y., Pamunuwa, D. B., Weerasekera, R., Zhonghai, L., Jantsch, A., & Shippen, D. (2009). Physical Mapping and Performance Study of a Multi-Clock 3-Dimensional Network-on-Chip Mesh. In Proceedings of the IEEE International Conference on 3D System Integration (3D IC), 2009 IEEE. https://doi.org/10.1109/3DIC.2009.5306540

Vancouver

Grange M, Weldezion AY, Pamunuwa DB, Weerasekera R, Zhonghai L, Jantsch A et al. Physical Mapping and Performance Study of a Multi-Clock 3-Dimensional Network-on-Chip Mesh. In Proceedings of the IEEE International Conference on 3D System Integration (3D IC), 2009. San Francisco: IEEE. 2009 doi: 10.1109/3DIC.2009.5306540

Author

Grange, M. ; Weldezion, A. Y. ; Pamunuwa, Dinesh Bandara et al. / Physical Mapping and Performance Study of a Multi-Clock 3-Dimensional Network-on-Chip Mesh. Proceedings of the IEEE International Conference on 3D System Integration (3D IC), 2009. San Francisco : IEEE, 2009.

Bibtex

@inbook{b37ccf9da5b74d8daebe01e4aee68cb9,
title = "Physical Mapping and Performance Study of a Multi-Clock 3-Dimensional Network-on-Chip Mesh.",
abstract = "The physical performance of a 3-Dimensional Network-on-Chip (NoC) mesh architecture employing through silicon vias (TSV) for vertical connectivity is investigated with a cycle-accurate RTL simulator. The physical latency and area impact of TSVs, switches, and the on-chip interconnect is evaluated to extract the maximum signaling speeds through the switches, horizontal and vertical network links. The relatively low parasitics of TSVs compared to the on-chip 2-D interconnect allow for higher signaling speeds between chip layers. The system-level impact on overall network performance as a result of clocking vertical packets at a higher rate through the TSV interconnect is simulated and reported.",
author = "M. Grange and Weldezion, {A. Y.} and Pamunuwa, {Dinesh Bandara} and R. Weerasekera and Lu Zhonghai and A. Jantsch and D. Shippen",
year = "2009",
doi = "10.1109/3DIC.2009.5306540",
language = "English",
isbn = "978-1-4244-4511-0",
booktitle = "Proceedings of the IEEE International Conference on 3D System Integration (3D IC), 2009",
publisher = "IEEE",

}

RIS

TY - CHAP

T1 - Physical Mapping and Performance Study of a Multi-Clock 3-Dimensional Network-on-Chip Mesh.

AU - Grange, M.

AU - Weldezion, A. Y.

AU - Pamunuwa, Dinesh Bandara

AU - Weerasekera, R.

AU - Zhonghai, Lu

AU - Jantsch, A.

AU - Shippen, D.

PY - 2009

Y1 - 2009

N2 - The physical performance of a 3-Dimensional Network-on-Chip (NoC) mesh architecture employing through silicon vias (TSV) for vertical connectivity is investigated with a cycle-accurate RTL simulator. The physical latency and area impact of TSVs, switches, and the on-chip interconnect is evaluated to extract the maximum signaling speeds through the switches, horizontal and vertical network links. The relatively low parasitics of TSVs compared to the on-chip 2-D interconnect allow for higher signaling speeds between chip layers. The system-level impact on overall network performance as a result of clocking vertical packets at a higher rate through the TSV interconnect is simulated and reported.

AB - The physical performance of a 3-Dimensional Network-on-Chip (NoC) mesh architecture employing through silicon vias (TSV) for vertical connectivity is investigated with a cycle-accurate RTL simulator. The physical latency and area impact of TSVs, switches, and the on-chip interconnect is evaluated to extract the maximum signaling speeds through the switches, horizontal and vertical network links. The relatively low parasitics of TSVs compared to the on-chip 2-D interconnect allow for higher signaling speeds between chip layers. The system-level impact on overall network performance as a result of clocking vertical packets at a higher rate through the TSV interconnect is simulated and reported.

U2 - 10.1109/3DIC.2009.5306540

DO - 10.1109/3DIC.2009.5306540

M3 - Chapter

SN - 978-1-4244-4511-0

BT - Proceedings of the IEEE International Conference on 3D System Integration (3D IC), 2009

PB - IEEE

CY - San Francisco

ER -