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Research output: Contribution to Journal/Magazine › Journal article › peer-review
Research output: Contribution to Journal/Magazine › Journal article › peer-review
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TY - JOUR
T1 - RD53 pixel readout integrated circuits for ATLAS and CMS HL-LHC upgrades
AU - The RD53 collaboration
AU - Alimonti, G.
AU - Andreazza, A.
AU - Arteche, F.
AU - Barbero, M.B.
AU - Barrillon, P.
AU - Beccherle, R.
AU - Bonomelli, G.
AU - Bilei, G.M.
AU - Bialas, W.
AU - Bortoletto, D.
AU - Calderini, G.
AU - Caratelli, A.
AU - Cassese, A.
AU - Christiansen, J.
AU - Conti, E.
AU - Crescioli, F.
AU - Daas, M.
AU - Damenti, L.
AU - D'Auria, S.
AU - De Canio, F.
AU - De Robertis, G.
AU - Demaria, N.
AU - DeWitt, J.
AU - Dieter, Y.
AU - Dimitrievska, A.
AU - Erdmann, W.
AU - Esposito, S.
AU - Exarchou, D.
AU - Fougeron, D.
AU - Gaioni, L.
AU - Garcia-Sciveres, M.
AU - Gnani, D.
AU - Gozalez Renteria, C.
AU - Grippo, M.
AU - Guardino, A.
AU - Hamer, M.
AU - Heim, T.
AU - Hemperek, T.
AU - Hinterkeuser, F.
AU - Huiberts, S.
AU - Jara Casas, L.M.
AU - John, J.J.
AU - Kampkötter, J.
AU - Karagounis, M.
AU - Kazas, I.
AU - Khwaira, Y.
AU - Kluit, R.
AU - Koukola, D.
AU - Meng, Lingxin
AU - Thompson, E.
PY - 2025/3/31
Y1 - 2025/3/31
N2 - The RD53 collaboration has since 2013 developed new hybrid pixel detector chips with 50 × 50 μm2 pixels for the HL-LHC upgrades of the ATLAS and CMS experiments at CERN. A common architecture, design and verification framework has been developed to enable final pixel chips of different sizes to be designed, verified and tested to handle extreme hit rates of 3 GHz/cm2 (up to 12 GHz per chip) together with an increased trigger rate of 1 MHz and efficient readout of up to 5.12 Gbits/s per pixel chip. Tolerance to an extremely hostile radiation environment with 1 Grad over 10 years and induced SEU (Single Event Upset) rates of up to 100 upsets per second per chip have been major challenges to make reliable pixel chips. Three generations of pixel chips, and many specific mixed signal building blocks and radiation test chips, have been submitted and extensively tested to get to final production chips. The large, complex and high rate pixel chips have been developed with a strong emphasis on low power consumption together with a concurrent development and qualification of novel serial powering at chip, module and system level, to minimize detector material budget.
AB - The RD53 collaboration has since 2013 developed new hybrid pixel detector chips with 50 × 50 μm2 pixels for the HL-LHC upgrades of the ATLAS and CMS experiments at CERN. A common architecture, design and verification framework has been developed to enable final pixel chips of different sizes to be designed, verified and tested to handle extreme hit rates of 3 GHz/cm2 (up to 12 GHz per chip) together with an increased trigger rate of 1 MHz and efficient readout of up to 5.12 Gbits/s per pixel chip. Tolerance to an extremely hostile radiation environment with 1 Grad over 10 years and induced SEU (Single Event Upset) rates of up to 100 upsets per second per chip have been major challenges to make reliable pixel chips. Three generations of pixel chips, and many specific mixed signal building blocks and radiation test chips, have been submitted and extensively tested to get to final production chips. The large, complex and high rate pixel chips have been developed with a strong emphasis on low power consumption together with a concurrent development and qualification of novel serial powering at chip, module and system level, to minimize detector material budget.
KW - Radiation-hard electronics
KW - VLSI circuits
KW - Particle tracking detectors (Solid-state detectors)
KW - Front-end electronics for detector readout
U2 - 10.1088/1748-0221/20/03/p03024
DO - 10.1088/1748-0221/20/03/p03024
M3 - Journal article
VL - 20
JO - Journal of Instrumentation
JF - Journal of Instrumentation
SN - 1748-0221
IS - 03
M1 - P03024
ER -