Home > Research > Publications & Outputs > Scalability of Network-on-Chip communication ar...

Research

Electronic data

Links

Text available via DOI:

View graph of relations

Scalability of Network-on-Chip communication architecture for 3-D meshes.

Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

Published

Standard

Scalability of Network-on-Chip communication architecture for 3-D meshes. / Weldezion, A. Y.; Grange, M.; Pamunuwa, Dinesh Bandara et al.
Proc. ACM/IEEE International Symposium on Networks on Chip (NOCS). San Diego: IEEE, 2009. p. 114-123.

Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

Harvard

Weldezion, AY, Grange, M, Pamunuwa, DB, Lu, Z, Jantsch, A, Weerasekera, R & Tenhunen, H 2009, Scalability of Network-on-Chip communication architecture for 3-D meshes. in Proc. ACM/IEEE International Symposium on Networks on Chip (NOCS). IEEE, San Diego, pp. 114-123. https://doi.org/10.1109/NOCS.2009.5071459

APA

Weldezion, A. Y., Grange, M., Pamunuwa, D. B., Lu, Z., Jantsch, A., Weerasekera, R., & Tenhunen, H. (2009). Scalability of Network-on-Chip communication architecture for 3-D meshes. In Proc. ACM/IEEE International Symposium on Networks on Chip (NOCS) (pp. 114-123). IEEE. https://doi.org/10.1109/NOCS.2009.5071459

Vancouver

Weldezion AY, Grange M, Pamunuwa DB, Lu Z, Jantsch A, Weerasekera R et al. Scalability of Network-on-Chip communication architecture for 3-D meshes. In Proc. ACM/IEEE International Symposium on Networks on Chip (NOCS). San Diego: IEEE. 2009. p. 114-123 doi: 10.1109/NOCS.2009.5071459

Author

Weldezion, A. Y. ; Grange, M. ; Pamunuwa, Dinesh Bandara et al. / Scalability of Network-on-Chip communication architecture for 3-D meshes. Proc. ACM/IEEE International Symposium on Networks on Chip (NOCS). San Diego : IEEE, 2009. pp. 114-123

Bibtex

@inbook{4683c6f272f44285827ed5fc9d473c25,
title = "Scalability of Network-on-Chip communication architecture for 3-D meshes.",
abstract = "Design constraints imposed by global interconnect delays as well as limitations in integration of disparate technologies make 3D chip stacks an enticing technology solution for massively integrated electronic systems. The scarcity of vertical interconnects however imposes special constraints on the design of the communication architecture. This article examines the performance and scalability of different communication topologies for 3D network-on-chips (NoC) using through-silicon-vias (TSV) for inter-die connectivity. Cycle accurate RTL-level simulations are conducted for two communication schemes based on a 7-port switch and a centrally arbitrated vertical bus using different traffic patterns. The scalability of the 3D NoC is examined under both communication architectures and compared to 2D NoC structures in terms of throughput and latency in order to quantify the variation of network performance with the number of nodes and derive key design guidelines.",
author = "Weldezion, {A. Y.} and M. Grange and Pamunuwa, {Dinesh Bandara} and Zhonghai Lu and A. Jantsch and Roshan Weerasekera and Hannu Tenhunen",
note = "{"}{\textcopyright}2009 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.{"} {"}This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.{"}",
year = "2009",
month = jun,
day = "12",
doi = "10.1109/NOCS.2009.5071459",
language = "English",
isbn = "978-1-4244-4142-6",
pages = "114--123",
booktitle = "Proc. ACM/IEEE International Symposium on Networks on Chip (NOCS)",
publisher = "IEEE",

}

RIS

TY - CHAP

T1 - Scalability of Network-on-Chip communication architecture for 3-D meshes.

AU - Weldezion, A. Y.

AU - Grange, M.

AU - Pamunuwa, Dinesh Bandara

AU - Lu, Zhonghai

AU - Jantsch, A.

AU - Weerasekera, Roshan

AU - Tenhunen, Hannu

N1 - "©2009 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE." "This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder."

PY - 2009/6/12

Y1 - 2009/6/12

N2 - Design constraints imposed by global interconnect delays as well as limitations in integration of disparate technologies make 3D chip stacks an enticing technology solution for massively integrated electronic systems. The scarcity of vertical interconnects however imposes special constraints on the design of the communication architecture. This article examines the performance and scalability of different communication topologies for 3D network-on-chips (NoC) using through-silicon-vias (TSV) for inter-die connectivity. Cycle accurate RTL-level simulations are conducted for two communication schemes based on a 7-port switch and a centrally arbitrated vertical bus using different traffic patterns. The scalability of the 3D NoC is examined under both communication architectures and compared to 2D NoC structures in terms of throughput and latency in order to quantify the variation of network performance with the number of nodes and derive key design guidelines.

AB - Design constraints imposed by global interconnect delays as well as limitations in integration of disparate technologies make 3D chip stacks an enticing technology solution for massively integrated electronic systems. The scarcity of vertical interconnects however imposes special constraints on the design of the communication architecture. This article examines the performance and scalability of different communication topologies for 3D network-on-chips (NoC) using through-silicon-vias (TSV) for inter-die connectivity. Cycle accurate RTL-level simulations are conducted for two communication schemes based on a 7-port switch and a centrally arbitrated vertical bus using different traffic patterns. The scalability of the 3D NoC is examined under both communication architectures and compared to 2D NoC structures in terms of throughput and latency in order to quantify the variation of network performance with the number of nodes and derive key design guidelines.

U2 - 10.1109/NOCS.2009.5071459

DO - 10.1109/NOCS.2009.5071459

M3 - Chapter

SN - 978-1-4244-4142-6

SP - 114

EP - 123

BT - Proc. ACM/IEEE International Symposium on Networks on Chip (NOCS)

PB - IEEE

CY - San Diego

ER -