TY - JOUR

T1 - Simulations of resonant tunnelling through InAs/AlSb heterostructures for ULTRARAM™ memory

AU - Lane, Dominic

AU - Hayne, Manus

PY - 2021/6/22

Y1 - 2021/6/22

N2 - ULTRARAM™ is a III–V semiconductor memory technology which allows non-volatile logic switching at ultra-low energy (per unit area). This is achieved by exploiting triple-barrier resonant tunnelling (TBRT) through a series of InAs/AlSb heterojunctions specifically engineered for this purpose. Electrons tunnelling through the barriers at low bias are trapped in a floating gate, in which the presence or absence of charge defines the memory logic. Here, we report detailed non-equilibrium Green's functions simulations of the InAs/AlSb TBRT heterostructure, which is the principal source of ULTRARAM™'s extraordinary performance benefits. The effects of variations to the heterostructure layer thickness are investigated for performance optimization, and for assessing growth and process tolerances for commercial implementation on 12'' Si wafers. Trade-offs between power, speed, logic disturbance and data retention time are identified. Importantly, most one monolayer alterations to the tunnelling region show the required characteristics for ULTRARAM™ memory operation, thus some tolerance in any future commercial fabrication process is identified.

AB - ULTRARAM™ is a III–V semiconductor memory technology which allows non-volatile logic switching at ultra-low energy (per unit area). This is achieved by exploiting triple-barrier resonant tunnelling (TBRT) through a series of InAs/AlSb heterojunctions specifically engineered for this purpose. Electrons tunnelling through the barriers at low bias are trapped in a floating gate, in which the presence or absence of charge defines the memory logic. Here, we report detailed non-equilibrium Green's functions simulations of the InAs/AlSb TBRT heterostructure, which is the principal source of ULTRARAM™'s extraordinary performance benefits. The effects of variations to the heterostructure layer thickness are investigated for performance optimization, and for assessing growth and process tolerances for commercial implementation on 12'' Si wafers. Trade-offs between power, speed, logic disturbance and data retention time are identified. Importantly, most one monolayer alterations to the tunnelling region show the required characteristics for ULTRARAM™ memory operation, thus some tolerance in any future commercial fabrication process is identified.

U2 - 10.1088/1361-6463/ac0a09

DO - 10.1088/1361-6463/ac0a09

M3 - Journal article

VL - 54

JO - Journal of Physics D: Applied Physics

JF - Journal of Physics D: Applied Physics

SN - 0022-3727

IS - 35

M1 - 335104

ER -