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Translating Structural Process Properties to Petri Net Markings

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Translating Structural Process Properties to Petri Net Markings. / Linker, Sven.
2012 12th International Conference on Application of Concurrency to System Design. IEEE, 2012.

Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Conference contribution/Paper › peer-review

Harvard

Linker, S 2012, Translating Structural Process Properties to Petri Net Markings. in 2012 12th International Conference on Application of Concurrency to System Design. IEEE. https://doi.org/10.1109/ACSD.2012.11

APA

Linker, S. (2012). Translating Structural Process Properties to Petri Net Markings. In 2012 12th International Conference on Application of Concurrency to System Design IEEE. https://doi.org/10.1109/ACSD.2012.11

Vancouver

Linker S. Translating Structural Process Properties to Petri Net Markings. In 2012 12th International Conference on Application of Concurrency to System Design. IEEE. 2012 Epub 2012 Jun 27. doi: 10.1109/ACSD.2012.11

Author

Linker, Sven. / Translating Structural Process Properties to Petri Net Markings. 2012 12th International Conference on Application of Concurrency to System Design. IEEE, 2012.

Bibtex

@inproceedings{97d1d501638e41a18a48590d909e62db,
title = "Translating Structural Process Properties to Petri Net Markings",
abstract = "We introduce a spatio-temporal logic PSTL defined on Pi-Calculus processes. This logic is especially suited to formulate properties in relation to the structural semantics of the Pi-Calculus due to Meyer, a representation of processes as Petri nets. To allow for the use of well-researched verification techniques, we present a translation of a subset of PSTL to LTL on Petri nets. We further prove soundness of our translation.",
author = "Sven Linker",
year = "2012",
month = aug,
day = "2",
doi = "10.1109/ACSD.2012.11",
language = "English",
isbn = "9781467316873",
booktitle = "2012 12th International Conference on Application of Concurrency to System Design",
publisher = "IEEE",

}

RIS

TY - GEN

T1 - Translating Structural Process Properties to Petri Net Markings

AU - Linker, Sven

PY - 2012/8/2

Y1 - 2012/8/2

N2 - We introduce a spatio-temporal logic PSTL defined on Pi-Calculus processes. This logic is especially suited to formulate properties in relation to the structural semantics of the Pi-Calculus due to Meyer, a representation of processes as Petri nets. To allow for the use of well-researched verification techniques, we present a translation of a subset of PSTL to LTL on Petri nets. We further prove soundness of our translation.

AB - We introduce a spatio-temporal logic PSTL defined on Pi-Calculus processes. This logic is especially suited to formulate properties in relation to the structural semantics of the Pi-Calculus due to Meyer, a representation of processes as Petri nets. To allow for the use of well-researched verification techniques, we present a translation of a subset of PSTL to LTL on Petri nets. We further prove soundness of our translation.

U2 - 10.1109/ACSD.2012.11

DO - 10.1109/ACSD.2012.11

M3 - Conference contribution/Paper

SN - 9781467316873

BT - 2012 12th International Conference on Application of Concurrency to System Design

PB - IEEE

ER -