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Using signed digit arithmetic for low-power multiplication

Research output: Contribution to Journal/MagazineJournal articlepeer-review

<mark>Journal publication date</mark>24/05/2007
<mark>Journal</mark>Electronics Letters
Issue number11
Number of pages2
Pages (from-to)613-614
Publication StatusPublished
<mark>Original language</mark>English


Hardware implementations of arithmetic operators using signed digit arithmetic have lost some of their earlier popularity. However, SD is revisited and used to realise an efficient radix-16 generic multiplier, which has particular potential for low-power implementation. The SD multiplier algorithm reduces the number of partial products to as much as 1/4, and in initial tests reduces the estimated power consumption to only about 50% of that of the Booth multiplier. It is different from other previous high-radix methods in that it employs a novel method to generate its partial products with zero arithmetic logic.