TY - JOUR

T1 - Using signed digit arithmetic for low-power multiplication

AU - Crookes, D.

AU - Jiang, M.

PY - 2007/5/24

Y1 - 2007/5/24

N2 - Hardware implementations of arithmetic operators using signed digit arithmetic have lost some of their earlier popularity. However, SD is revisited and used to realise an efficient radix-16 generic multiplier, which has particular potential for low-power implementation. The SD multiplier algorithm reduces the number of partial products to as much as 1/4, and in initial tests reduces the estimated power consumption to only about 50% of that of the Booth multiplier. It is different from other previous high-radix methods in that it employs a novel method to generate its partial products with zero arithmetic logic.

AB - Hardware implementations of arithmetic operators using signed digit arithmetic have lost some of their earlier popularity. However, SD is revisited and used to realise an efficient radix-16 generic multiplier, which has particular potential for low-power implementation. The SD multiplier algorithm reduces the number of partial products to as much as 1/4, and in initial tests reduces the estimated power consumption to only about 50% of that of the Booth multiplier. It is different from other previous high-radix methods in that it employs a novel method to generate its partial products with zero arithmetic logic.

KW - signed digit arithmetic

KW - low-power multiplication

KW - arithmetic operators

KW - radix-16 generic multiplier

KW - SD multiplier algorithm

KW - power consumption

KW - Booth multiplier

KW - zero arithmetic logic

U2 - 10.1049/el:20070761

DO - 10.1049/el:20070761

M3 - Journal article

VL - 43

SP - 613

EP - 614

JO - Electronics Letters

JF - Electronics Letters

SN - 0013-5194

IS - 11

ER -