Final published version
Licence: CC BY: Creative Commons Attribution 4.0 International License
Research output: Contribution to Journal/Magazine › Journal article › peer-review
Article number | 20160043 |
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<mark>Journal publication date</mark> | 26/02/2016 |
<mark>Journal</mark> | IEICE Electronics Express |
Issue number | 6 |
Volume | 13 |
Publication Status | Published |
<mark>Original language</mark> | English |
This paper presents a parametrized VLSI architecture for an nstate Kalman filter implementation intended for real-time applications that typically require a sensing rate not far from 300 samples per second. The architecture has been optimized in silicon area and power consumption. This approach has been proved with a fabricated chip using a 0.5μm CMOS technology. The fabricated integrated circuit executes a two-state Kalman filter employing 70K transistors. For a performance of 50 filter iterations/second, the chip requires a clock frequency of 200 KHz where a negligible power consumption of 1.1mWis observed. This performance can be increased up to 176,991 iterations/second at a clock frequency of 20 MHz.