TY - JOUR

T1 - VLSI architecture of a Kalman filter optimized for real-time applications

AU - Chávez-Bracamontes, Ramón

AU - Gurrola-Navarro, Marco A.

AU - Jiménez-Flores, Humberto J.

AU - Bandala-Sánchez, Manuel

PY - 2016/2/26

Y1 - 2016/2/26

N2 - This paper presents a parametrized VLSI architecture for an nstate Kalman filter implementation intended for real-time applications that typically require a sensing rate not far from 300 samples per second. The architecture has been optimized in silicon area and power consumption. This approach has been proved with a fabricated chip using a 0.5μm CMOS technology. The fabricated integrated circuit executes a two-state Kalman filter employing 70K transistors. For a performance of 50 filter iterations/second, the chip requires a clock frequency of 200 KHz where a negligible power consumption of 1.1mWis observed. This performance can be increased up to 176,991 iterations/second at a clock frequency of 20 MHz.

AB - This paper presents a parametrized VLSI architecture for an nstate Kalman filter implementation intended for real-time applications that typically require a sensing rate not far from 300 samples per second. The architecture has been optimized in silicon area and power consumption. This approach has been proved with a fabricated chip using a 0.5μm CMOS technology. The fabricated integrated circuit executes a two-state Kalman filter employing 70K transistors. For a performance of 50 filter iterations/second, the chip requires a clock frequency of 200 KHz where a negligible power consumption of 1.1mWis observed. This performance can be increased up to 176,991 iterations/second at a clock frequency of 20 MHz.

KW - CMOS

KW - Kalman filter

KW - On-chip algorithm

KW - VLSI

U2 - 10.1587/elex.13.20160043

DO - 10.1587/elex.13.20160043

M3 - Journal article

AN - SCOPUS:84961718541

VL - 13

JO - IEICE Electronics Express

JF - IEICE Electronics Express

SN - 1349-2543

IS - 6

M1 - 20160043

ER -