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Dr Roshan Weerasekera

Formerly at Lancaster University

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  1. Published

    Minimal-power, delay-balanced smart repeaters for interconnects in the nanometer regime.

    Weerasekera, R., Pamunuwa, D. B., Zheng, L-R. & Tenhunen, H., 03/2006, Proc. International Workshop on System-level Interconnect Prediction (SLIP). Munich: ACM, p. 113-120 8 p.

    Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

  2. Published

    On signalling over through-silicon via (TSV) interconnects in 3-D integrated circuits.

    Weerasekera, R., Grange, M., Pamunuwa, D. B. & Tenhunen, H., 03/2010, p. 1325-1328. 4 p.

    Research output: Contribution to conference - Without ISBN/ISSN › Conference paper › peer-review

  3. Published

    Compact modelling of through-silicon vias (TSVs) in three-dimensional (3-D) integrated circuits.

    Weerasekera, R., Grange, M., Pamunuwa, D. B., Tenhunen, H. & Zheng, L-R., 10/2009, Proceedings of the IEEE International Conference on 3D System Integration (3D IC), 2009. San Francisco: IEEE

    Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

  4. Published

    Switching sensitive driver circuit to combat dynamic delay in on-chip buses

    Weerasekera, R., Zheng, L-R., Pamunuwa, D. B., Tenhunen, H., Paliouras, V. (ed.), Vounckx, J. (ed.) & Verkest, D. (ed.), 09/2005, Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation: 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005. Proceedings. Paliouras, V., Vounckx, J. & Verkest, D. (eds.). Berlin: Springer, p. 277-285 9 p. (Lecture Notes in Computer Science; vol. 3728).

    Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

  5. Published

    Scalability of Network-on-Chip communication architecture for 3-D meshes.

    Weldezion, A. Y., Grange, M., Pamunuwa, D. B., Lu, Z., Jantsch, A., Weerasekera, R. & Tenhunen, H., 12/06/2009, Proc. ACM/IEEE International Symposium on Networks on Chip (NOCS). San Diego: IEEE, p. 114-123 10 p.

    Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

  6. Published

    Bandwidth optimization for through silicon via (TSV) bundles in 3D integrated circuits.

    Weldezion, A., Weerasekera, R., Pamunuwa, D. B., Zheng, L-R. & Tenhunen, H., 2009, Workshop Notes, Design, Automation and Test in Europe (DATE). Nice

    Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

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