Home > Research > Publications & Outputs > Switching sensitive driver circuit to combat dy...
View graph of relations

Switching sensitive driver circuit to combat dynamic delay in on-chip buses

Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSNChapter

Published
Close
Publication date09/2005
Host publicationIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation: 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005. Proceedings
EditorsVassilis Paliouras, Johan Vounckx, Diederik Verkest
Place of PublicationBerlin
PublisherSpringer
Pages277-285
Number of pages9
ISBN (electronic)9783540320807
ISBN (print)9783540290131
<mark>Original language</mark>English

Publication series

NameLecture Notes in Computer Science
PublisherSpringer
Volume3728
ISSN (Print)0302-9743
ISSN (electronic)1611-3349

Abstract

In this paper, we propose a novel Interconnect Driver circuit scheme for on-chip bus structures, which changes it’s drive strength based on the switching pattern of the neighbouring interconnect. The circuit is quite simple compared to driver circuits proposed in the literature. The results show that for the cost of a few transistors, the proposed driver circuit has a wider eye opening (upto a 100% improvement) and reduced jitter (up to a 32% reduction) than a traditional driver for typical DSM technologies.