Research output: Contribution to Journal/Magazine › Journal article › peer-review
Article number | 063503 |
---|---|
<mark>Journal publication date</mark> | 12/08/2015 |
<mark>Journal</mark> | Applied Physics Letters |
Issue number | 6 |
Volume | 107 |
Number of pages | 5 |
Publication Status | Published |
<mark>Original language</mark> | English |
Schottky Barrier-MOSFET technology offers intriguing possibilities for cryogenic nano-scale devices, such as Si quantum devices and superconducting devices. We present experimental results on a device architecture where the gate electrode is self-aligned with the device channel and overlaps the source and drain electrodes. This facilitates a sub-5 nm gap between the source/drain and channel, and no spacers are required. At cryogenic temperatures, such devices function as p-MOS Tunnel FETs, as determined by the Schottky barrier at the Al-Si interface, and as a further advantage, fabrication processes are compatible with both CMOS and superconducting logic technology.