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A planar Al-Si Schottky barrier metal-oxide-semiconductor field effect transistor operated at cryogenic temperatures

Research output: Contribution to Journal/Magazine › Journal article › peer-review

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A planar Al-Si Schottky barrier metal-oxide-semiconductor field effect transistor operated at cryogenic temperatures. / Purches, W. E.; Rossi, A.; Zhao, R. et al.
In: Applied Physics Letters, Vol. 107, No. 6, 063503, 12.08.2015.

Research output: Contribution to Journal/Magazine › Journal article › peer-review

Harvard

Purches, WE, Rossi, A, Zhao, R, Kafanov, S, Duty, TL, Dzurak, AS, Rogge, S & Tettamanzi, GC 2015, 'A planar Al-Si Schottky barrier metal-oxide-semiconductor field effect transistor operated at cryogenic temperatures', Applied Physics Letters, vol. 107, no. 6, 063503. https://doi.org/10.1063/1.4928589

APA

Purches, W. E., Rossi, A., Zhao, R., Kafanov, S., Duty, T. L., Dzurak, A. S., Rogge, S., & Tettamanzi, G. C. (2015). A planar Al-Si Schottky barrier metal-oxide-semiconductor field effect transistor operated at cryogenic temperatures. Applied Physics Letters, 107(6), Article 063503. https://doi.org/10.1063/1.4928589

Vancouver

Purches WE, Rossi A, Zhao R, Kafanov S, Duty TL, Dzurak AS et al. A planar Al-Si Schottky barrier metal-oxide-semiconductor field effect transistor operated at cryogenic temperatures. Applied Physics Letters. 2015 Aug 12;107(6):063503. doi: 10.1063/1.4928589

Author

Purches, W. E. ; Rossi, A. ; Zhao, R. et al. / A planar Al-Si Schottky barrier metal-oxide-semiconductor field effect transistor operated at cryogenic temperatures. In: Applied Physics Letters. 2015 ; Vol. 107, No. 6.

Bibtex

@article{af73ac6077784787be879d36b8713aed,
title = "A planar Al-Si Schottky barrier metal-oxide-semiconductor field effect transistor operated at cryogenic temperatures",
abstract = "Schottky Barrier-MOSFET technology offers intriguing possibilities for cryogenic nano-scale devices, such as Si quantum devices and superconducting devices. We present experimental results on a device architecture where the gate electrode is self-aligned with the device channel and overlaps the source and drain electrodes. This facilitates a sub-5 nm gap between the source/drain and channel, and no spacers are required. At cryogenic temperatures, such devices function as p-MOS Tunnel FETs, as determined by the Schottky barrier at the Al-Si interface, and as a further advantage, fabrication processes are compatible with both CMOS and superconducting logic technology.",
author = "Purches, {W. E.} and A. Rossi and R. Zhao and Sergey Kafanov and Duty, {T. L.} and Dzurak, {A. S.} and S. Rogge and Tettamanzi, {G. C.}",
year = "2015",
month = aug,
day = "12",
doi = "10.1063/1.4928589",
language = "English",
volume = "107",
journal = "Applied Physics Letters",
issn = "0003-6951",
publisher = "American Institute of Physics Inc.",
number = "6",

}

RIS

TY - JOUR

T1 - A planar Al-Si Schottky barrier metal-oxide-semiconductor field effect transistor operated at cryogenic temperatures

AU - Purches, W. E.

AU - Rossi, A.

AU - Zhao, R.

AU - Kafanov, Sergey

AU - Duty, T. L.

AU - Dzurak, A. S.

AU - Rogge, S.

AU - Tettamanzi, G. C.

PY - 2015/8/12

Y1 - 2015/8/12

N2 - Schottky Barrier-MOSFET technology offers intriguing possibilities for cryogenic nano-scale devices, such as Si quantum devices and superconducting devices. We present experimental results on a device architecture where the gate electrode is self-aligned with the device channel and overlaps the source and drain electrodes. This facilitates a sub-5 nm gap between the source/drain and channel, and no spacers are required. At cryogenic temperatures, such devices function as p-MOS Tunnel FETs, as determined by the Schottky barrier at the Al-Si interface, and as a further advantage, fabrication processes are compatible with both CMOS and superconducting logic technology.

AB - Schottky Barrier-MOSFET technology offers intriguing possibilities for cryogenic nano-scale devices, such as Si quantum devices and superconducting devices. We present experimental results on a device architecture where the gate electrode is self-aligned with the device channel and overlaps the source and drain electrodes. This facilitates a sub-5 nm gap between the source/drain and channel, and no spacers are required. At cryogenic temperatures, such devices function as p-MOS Tunnel FETs, as determined by the Schottky barrier at the Al-Si interface, and as a further advantage, fabrication processes are compatible with both CMOS and superconducting logic technology.

U2 - 10.1063/1.4928589

DO - 10.1063/1.4928589

M3 - Journal article

AN - SCOPUS:84939142008

VL - 107

JO - Applied Physics Letters

JF - Applied Physics Letters

SN - 0003-6951

IS - 6

M1 - 063503

ER -