Standard
Harvard
Weldezion, A
, Weerasekera, R, Pamunuwa, DB, Zheng, L-R & Tenhunen, H 2009,
Bandwidth optimization for through silicon via (TSV) bundles in 3D integrated circuits. in
Workshop Notes, Design, Automation and Test in Europe (DATE). Nice.
APA
Weldezion, A.
, Weerasekera, R., Pamunuwa, D. B., Zheng, L.-R., & Tenhunen, H. (2009).
Bandwidth optimization for through silicon via (TSV) bundles in 3D integrated circuits. In
Workshop Notes, Design, Automation and Test in Europe (DATE) Vancouver
Author
Bibtex
@inbook{0b99a167d85f40ac98e041b9a50e1b3e,
title = "Bandwidth optimization for through silicon via (TSV) bundles in 3D integrated circuits.",
author = "A. Weldezion and Roshan Weerasekera and Pamunuwa, {Danesh B.} and Li-Rong Zheng and Hannu Tenhunen",
year = "2009",
language = "English",
booktitle = "Workshop Notes, Design, Automation and Test in Europe (DATE)",
}
RIS
TY - CHAP
T1 - Bandwidth optimization for through silicon via (TSV) bundles in 3D integrated circuits.
AU - Weldezion, A.
AU - Weerasekera, Roshan
AU - Pamunuwa, Danesh B.
AU - Zheng, Li-Rong
AU - Tenhunen, Hannu
PY - 2009
Y1 - 2009
M3 - Chapter
BT - Workshop Notes, Design, Automation and Test in Europe (DATE)
CY - Nice
ER -
