Delay-balanced smart repeaters for on-chip global signaling.
Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter
Published
| Publication date | 12/02/2007 |
|---|---|
| Host publication | Proc. International Conference on VLSI Design |
| Place of Publication | Bangalore |
| Publisher | IEEE |
| Pages | 308-313 |
| Number of pages | 6 |
| ISBN (print) | 0-7695-2762-0 |
| <mark>Original language</mark> | English |
Abstract
In this paper we propose a smart driver, whose drive strength is dynamically altered depending on the relative bit pattern, by partitioning it into a main driver and assistant driver. For a higher effective load capacitance both drivers switch, while for a lower effective capacitance the assistant driver is quiet. It is shown that in an UMC 0.18mum technology the potential peak power saving, for typical global wire lengths, can be as much 18% with a 12% jitter reduction over a traditional repeater for a data rate of 1Gb/s.
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