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Delay-balanced smart repeaters for on-chip global signaling.

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Delay-balanced smart repeaters for on-chip global signaling. / Weerasekera, Roshan; Pamunuwa, Dinesh B.; Zheng, Li-Rong et al.
Proc. International Conference on VLSI Design. Bangalore: IEEE, 2007. p. 308-313.

Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

Harvard

Weerasekera, R, Pamunuwa, DB, Zheng, L-R & Tenhunen, H 2007, Delay-balanced smart repeaters for on-chip global signaling. in Proc. International Conference on VLSI Design. IEEE, Bangalore, pp. 308-313. https://doi.org/10.1109/VLSID.2007.62

APA

Weerasekera, R., Pamunuwa, D. B., Zheng, L.-R., & Tenhunen, H. (2007). Delay-balanced smart repeaters for on-chip global signaling. In Proc. International Conference on VLSI Design (pp. 308-313). IEEE. https://doi.org/10.1109/VLSID.2007.62

Vancouver

Weerasekera R, Pamunuwa DB, Zheng LR, Tenhunen H. Delay-balanced smart repeaters for on-chip global signaling. In Proc. International Conference on VLSI Design. Bangalore: IEEE. 2007. p. 308-313 doi: 10.1109/VLSID.2007.62

Author

Weerasekera, Roshan ; Pamunuwa, Dinesh B. ; Zheng, Li-Rong et al. / Delay-balanced smart repeaters for on-chip global signaling. Proc. International Conference on VLSI Design. Bangalore : IEEE, 2007. pp. 308-313

Bibtex

@inbook{660572e63c5c4fe7aad4a5567992e939,
title = "Delay-balanced smart repeaters for on-chip global signaling.",
abstract = "In this paper we propose a smart driver, whose drive strength is dynamically altered depending on the relative bit pattern, by partitioning it into a main driver and assistant driver. For a higher effective load capacitance both drivers switch, while for a lower effective capacitance the assistant driver is quiet. It is shown that in an UMC 0.18mum technology the potential peak power saving, for typical global wire lengths, can be as much 18% with a 12% jitter reduction over a traditional repeater for a data rate of 1Gb/s.",
author = "Roshan Weerasekera and Pamunuwa, {Dinesh B.} and Li-Rong Zheng and Hannu Tenhunen",
note = "{"}{\textcopyright}2007 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.{"} {"}This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.{"}",
year = "2007",
month = feb,
day = "12",
doi = "10.1109/VLSID.2007.62",
language = "English",
isbn = "0-7695-2762-0",
pages = "308--313",
booktitle = "Proc. International Conference on VLSI Design",
publisher = "IEEE",

}

RIS

TY - CHAP

T1 - Delay-balanced smart repeaters for on-chip global signaling.

AU - Weerasekera, Roshan

AU - Pamunuwa, Dinesh B.

AU - Zheng, Li-Rong

AU - Tenhunen, Hannu

N1 - "©2007 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE." "This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder."

PY - 2007/2/12

Y1 - 2007/2/12

N2 - In this paper we propose a smart driver, whose drive strength is dynamically altered depending on the relative bit pattern, by partitioning it into a main driver and assistant driver. For a higher effective load capacitance both drivers switch, while for a lower effective capacitance the assistant driver is quiet. It is shown that in an UMC 0.18mum technology the potential peak power saving, for typical global wire lengths, can be as much 18% with a 12% jitter reduction over a traditional repeater for a data rate of 1Gb/s.

AB - In this paper we propose a smart driver, whose drive strength is dynamically altered depending on the relative bit pattern, by partitioning it into a main driver and assistant driver. For a higher effective load capacitance both drivers switch, while for a lower effective capacitance the assistant driver is quiet. It is shown that in an UMC 0.18mum technology the potential peak power saving, for typical global wire lengths, can be as much 18% with a 12% jitter reduction over a traditional repeater for a data rate of 1Gb/s.

U2 - 10.1109/VLSID.2007.62

DO - 10.1109/VLSID.2007.62

M3 - Chapter

SN - 0-7695-2762-0

SP - 308

EP - 313

BT - Proc. International Conference on VLSI Design

PB - IEEE

CY - Bangalore

ER -