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Extending systems-on-chip to the third dimension : performance, cost and technological tradeoffs.

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Published
Publication date11/2007
Host publicationProc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
Place of PublicationSan Jose, California
PublisherIEEE
Pages212-219
Number of pages8
ISBN (print)978-1-4244-1382-9
<mark>Original language</mark>English

Abstract

Because of the today's market demand for high-performance, high-density portable hand-held applications, electronic system design technology has shifted the focus from 2-D planar SoC single-chip solutions to different alternative options as tiled silicon and single-level embedded modules as well as 3-D integration. Among the various choices, finding an optimal solution for system implementation dealt usually with cost, performance and other technological trade-off analysis at the system conceptual level. It has been identified that the decisions made within the first 20% of the total design cycle time will ultimately result up to 80% of the final product cost. In this paper, we discuss appropriate and realistic metric for performance and cost trade-off analysis both at system conceptual level (up-front in the design phase) and at implementation phase for verification in the three-dimensional integration. In order to validate the methodology, two ubiquitous electronic systems are analyzed under various implementation schemes and discuss the pros and cons of each of them.

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