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Extending systems-on-chip to the third dimension : performance, cost and technological tradeoffs.

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Extending systems-on-chip to the third dimension : performance, cost and technological tradeoffs. / Weerasekera, Roshan; Zheng, Li-Rong; Pamunuwa, Dinesh B. et al.
Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD). San Jose, California: IEEE, 2007. p. 212-219.

Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

Harvard

Weerasekera, R, Zheng, L-R, Pamunuwa, DB & Tenhunen, H 2007, Extending systems-on-chip to the third dimension : performance, cost and technological tradeoffs. in Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD). IEEE, San Jose, California, pp. 212-219. https://doi.org/10.1109/ICCAD.2007.4397268

APA

Weerasekera, R., Zheng, L.-R., Pamunuwa, D. B., & Tenhunen, H. (2007). Extending systems-on-chip to the third dimension : performance, cost and technological tradeoffs. In Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD) (pp. 212-219). IEEE. https://doi.org/10.1109/ICCAD.2007.4397268

Vancouver

Weerasekera R, Zheng LR, Pamunuwa DB, Tenhunen H. Extending systems-on-chip to the third dimension : performance, cost and technological tradeoffs. In Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD). San Jose, California: IEEE. 2007. p. 212-219 doi: 10.1109/ICCAD.2007.4397268

Author

Weerasekera, Roshan ; Zheng, Li-Rong ; Pamunuwa, Dinesh B. et al. / Extending systems-on-chip to the third dimension : performance, cost and technological tradeoffs. Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD). San Jose, California : IEEE, 2007. pp. 212-219

Bibtex

@inbook{a4166a05193b4c319b5e632cf628821f,
title = "Extending systems-on-chip to the third dimension : performance, cost and technological tradeoffs.",
abstract = "Because of the today's market demand for high-performance, high-density portable hand-held applications, electronic system design technology has shifted the focus from 2-D planar SoC single-chip solutions to different alternative options as tiled silicon and single-level embedded modules as well as 3-D integration. Among the various choices, finding an optimal solution for system implementation dealt usually with cost, performance and other technological trade-off analysis at the system conceptual level. It has been identified that the decisions made within the first 20% of the total design cycle time will ultimately result up to 80% of the final product cost. In this paper, we discuss appropriate and realistic metric for performance and cost trade-off analysis both at system conceptual level (up-front in the design phase) and at implementation phase for verification in the three-dimensional integration. In order to validate the methodology, two ubiquitous electronic systems are analyzed under various implementation schemes and discuss the pros and cons of each of them.",
author = "Roshan Weerasekera and Li-Rong Zheng and Pamunuwa, {Dinesh B.} and Hannu Tenhunen",
note = "{"}{\textcopyright}2007 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.{"} {"}This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.{"}",
year = "2007",
month = nov,
doi = "10.1109/ICCAD.2007.4397268",
language = "English",
isbn = "978-1-4244-1382-9",
pages = "212--219",
booktitle = "Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD)",
publisher = "IEEE",

}

RIS

TY - CHAP

T1 - Extending systems-on-chip to the third dimension : performance, cost and technological tradeoffs.

AU - Weerasekera, Roshan

AU - Zheng, Li-Rong

AU - Pamunuwa, Dinesh B.

AU - Tenhunen, Hannu

N1 - "©2007 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE." "This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder."

PY - 2007/11

Y1 - 2007/11

N2 - Because of the today's market demand for high-performance, high-density portable hand-held applications, electronic system design technology has shifted the focus from 2-D planar SoC single-chip solutions to different alternative options as tiled silicon and single-level embedded modules as well as 3-D integration. Among the various choices, finding an optimal solution for system implementation dealt usually with cost, performance and other technological trade-off analysis at the system conceptual level. It has been identified that the decisions made within the first 20% of the total design cycle time will ultimately result up to 80% of the final product cost. In this paper, we discuss appropriate and realistic metric for performance and cost trade-off analysis both at system conceptual level (up-front in the design phase) and at implementation phase for verification in the three-dimensional integration. In order to validate the methodology, two ubiquitous electronic systems are analyzed under various implementation schemes and discuss the pros and cons of each of them.

AB - Because of the today's market demand for high-performance, high-density portable hand-held applications, electronic system design technology has shifted the focus from 2-D planar SoC single-chip solutions to different alternative options as tiled silicon and single-level embedded modules as well as 3-D integration. Among the various choices, finding an optimal solution for system implementation dealt usually with cost, performance and other technological trade-off analysis at the system conceptual level. It has been identified that the decisions made within the first 20% of the total design cycle time will ultimately result up to 80% of the final product cost. In this paper, we discuss appropriate and realistic metric for performance and cost trade-off analysis both at system conceptual level (up-front in the design phase) and at implementation phase for verification in the three-dimensional integration. In order to validate the methodology, two ubiquitous electronic systems are analyzed under various implementation schemes and discuss the pros and cons of each of them.

U2 - 10.1109/ICCAD.2007.4397268

DO - 10.1109/ICCAD.2007.4397268

M3 - Chapter

SN - 978-1-4244-1382-9

SP - 212

EP - 219

BT - Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

PB - IEEE

CY - San Jose, California

ER -