Home > Research > Publications & Outputs > Feasibility demonstration of new e-NVM cells su...

Text available via DOI:

View graph of relations

Feasibility demonstration of new e-NVM cells suitable for integration at 28nm

Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSNConference contribution/Paperpeer-review

Published

Standard

Feasibility demonstration of new e-NVM cells suitable for integration at 28nm. / Tekin, Serdar B.
2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS). IEEE, 2017.

Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSNConference contribution/Paperpeer-review

Harvard

Tekin, SB 2017, Feasibility demonstration of new e-NVM cells suitable for integration at 28nm. in 2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS). IEEE. https://doi.org/10.1109/ulis.2017.7962599

APA

Tekin, S. B. (2017). Feasibility demonstration of new e-NVM cells suitable for integration at 28nm. In 2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) IEEE. https://doi.org/10.1109/ulis.2017.7962599

Vancouver

Tekin SB. Feasibility demonstration of new e-NVM cells suitable for integration at 28nm. In 2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS). IEEE. 2017 doi: 10.1109/ulis.2017.7962599

Author

Tekin, Serdar B. / Feasibility demonstration of new e-NVM cells suitable for integration at 28nm. 2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS). IEEE, 2017.

Bibtex

@inproceedings{337d36d3fbbc49d8a0fb5de0864041f6,
title = "Feasibility demonstration of new e-NVM cells suitable for integration at 28nm",
abstract = "Memory cell selection for 28 nm and beyond and its integration into new eNVM technology have been investigated through atomic layer deposition (ALD) HfO 2 resistive memory devices. Both amorphous and crystalline HfO 2 layers exhibit promising switching characteristics. It was shown that more than 3 times less power is required to activate the memory device fabricated using the amorphous layer. The forming voltages for both of the memory cell are greater than 10 Volt relative to layer thickness of 50 nm. As an alternative potential resistive memory element, SiOx layer formed on n and p type Si wafers exhibited interesting forming features.",
author = "Tekin, {Serdar B.}",
year = "2017",
month = jul,
day = "3",
doi = "10.1109/ulis.2017.7962599",
language = "English",
booktitle = "2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)",
publisher = "IEEE",

}

RIS

TY - GEN

T1 - Feasibility demonstration of new e-NVM cells suitable for integration at 28nm

AU - Tekin, Serdar B.

PY - 2017/7/3

Y1 - 2017/7/3

N2 - Memory cell selection for 28 nm and beyond and its integration into new eNVM technology have been investigated through atomic layer deposition (ALD) HfO 2 resistive memory devices. Both amorphous and crystalline HfO 2 layers exhibit promising switching characteristics. It was shown that more than 3 times less power is required to activate the memory device fabricated using the amorphous layer. The forming voltages for both of the memory cell are greater than 10 Volt relative to layer thickness of 50 nm. As an alternative potential resistive memory element, SiOx layer formed on n and p type Si wafers exhibited interesting forming features.

AB - Memory cell selection for 28 nm and beyond and its integration into new eNVM technology have been investigated through atomic layer deposition (ALD) HfO 2 resistive memory devices. Both amorphous and crystalline HfO 2 layers exhibit promising switching characteristics. It was shown that more than 3 times less power is required to activate the memory device fabricated using the amorphous layer. The forming voltages for both of the memory cell are greater than 10 Volt relative to layer thickness of 50 nm. As an alternative potential resistive memory element, SiOx layer formed on n and p type Si wafers exhibited interesting forming features.

U2 - 10.1109/ulis.2017.7962599

DO - 10.1109/ulis.2017.7962599

M3 - Conference contribution/Paper

BT - 2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)

PB - IEEE

ER -