Standard
Switching sensitive driver circuit to combat dynamic delay in on-chip buses. /
Weerasekera, Roshan; Zheng, Li-Rong
; Pamunuwa, Dinesh Bandara et al.
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation: 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005. Proceedings. ed. / Vassilis Paliouras; Johan Vounckx; Diederik Verkest. Berlin: Springer, 2005. p. 277-285 (Lecture Notes in Computer Science; Vol. 3728).
Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter
Harvard
Weerasekera, R, Zheng, L-R
, Pamunuwa, DB, Tenhunen, H, Paliouras, V (ed.), Vounckx, J (ed.) & Verkest, D (ed.) 2005,
Switching sensitive driver circuit to combat dynamic delay in on-chip buses. in V Paliouras, J Vounckx & D Verkest (eds),
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation: 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005. Proceedings. Lecture Notes in Computer Science, vol. 3728, Springer, Berlin, pp. 277-285.
https://doi.org/10.1007/11556930_29
APA
Weerasekera, R., Zheng, L-R.
, Pamunuwa, D. B., Tenhunen, H., Paliouras, V. (Ed.), Vounckx, J. (Ed.), & Verkest, D. (Ed.) (2005).
Switching sensitive driver circuit to combat dynamic delay in on-chip buses. In V. Paliouras, J. Vounckx, & D. Verkest (Eds.),
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation: 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005. Proceedings (pp. 277-285). (Lecture Notes in Computer Science; Vol. 3728). Springer.
https://doi.org/10.1007/11556930_29
Vancouver
Weerasekera R, Zheng L-R
, Pamunuwa DB, Tenhunen H, Paliouras V, (ed.), Vounckx J, (ed.) et al.
Switching sensitive driver circuit to combat dynamic delay in on-chip buses. In Paliouras V, Vounckx J, Verkest D, editors, Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation: 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005. Proceedings. Berlin: Springer. 2005. p. 277-285. (Lecture Notes in Computer Science). doi: 10.1007/11556930_29
Author
Weerasekera, Roshan ; Zheng, Li-Rong
; Pamunuwa, Dinesh Bandara et al. /
Switching sensitive driver circuit to combat dynamic delay in on-chip buses. Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation: 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005. Proceedings. editor / Vassilis Paliouras ; Johan Vounckx ; Diederik Verkest. Berlin : Springer, 2005. pp. 277-285 (Lecture Notes in Computer Science).
Bibtex
@inbook{024958fa937d474e9999cef4efba4807,
title = "Switching sensitive driver circuit to combat dynamic delay in on-chip buses",
abstract = "In this paper, we propose a novel Interconnect Driver circuit scheme for on-chip bus structures, which changes it{\textquoteright}s drive strength based on the switching pattern of the neighbouring interconnect. The circuit is quite simple compared to driver circuits proposed in the literature. The results show that for the cost of a few transistors, the proposed driver circuit has a wider eye opening (upto a 100% improvement) and reduced jitter (up to a 32% reduction) than a traditional driver for typical DSM technologies.",
author = "Roshan Weerasekera and Li-Rong Zheng and Pamunuwa, {Dinesh Bandara} and Hannu Tenhunen and V. Paliouras and J. Vounckx and D. Verkest",
year = "2005",
month = sep,
doi = "10.1007/11556930_29",
language = "English",
isbn = "9783540290131",
series = "Lecture Notes in Computer Science",
publisher = "Springer",
pages = "277--285",
editor = "Vassilis Paliouras and Johan Vounckx and Diederik Verkest",
booktitle = "Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation",
}
RIS
TY - CHAP
T1 - Switching sensitive driver circuit to combat dynamic delay in on-chip buses
AU - Weerasekera, Roshan
AU - Zheng, Li-Rong
AU - Pamunuwa, Dinesh Bandara
AU - Tenhunen, Hannu
A2 - Paliouras, V.
A2 - Vounckx, J.
A2 - Verkest, D.
A2 - Paliouras, Vassilis
A2 - Vounckx, Johan
A2 - Verkest, Diederik
PY - 2005/9
Y1 - 2005/9
N2 - In this paper, we propose a novel Interconnect Driver circuit scheme for on-chip bus structures, which changes it’s drive strength based on the switching pattern of the neighbouring interconnect. The circuit is quite simple compared to driver circuits proposed in the literature. The results show that for the cost of a few transistors, the proposed driver circuit has a wider eye opening (upto a 100% improvement) and reduced jitter (up to a 32% reduction) than a traditional driver for typical DSM technologies.
AB - In this paper, we propose a novel Interconnect Driver circuit scheme for on-chip bus structures, which changes it’s drive strength based on the switching pattern of the neighbouring interconnect. The circuit is quite simple compared to driver circuits proposed in the literature. The results show that for the cost of a few transistors, the proposed driver circuit has a wider eye opening (upto a 100% improvement) and reduced jitter (up to a 32% reduction) than a traditional driver for typical DSM technologies.
U2 - 10.1007/11556930_29
DO - 10.1007/11556930_29
M3 - Chapter
SN - 9783540290131
T3 - Lecture Notes in Computer Science
SP - 277
EP - 285
BT - Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
PB - Springer
CY - Berlin
ER -
