Rights statement: This is the author’s peer reviewed, accepted manuscript. However, the online version of record will be different from this version once it has been copyedited and typeset. PLEASE CITE THIS ARTICLE AS DOI: 10.1063/5.0268728
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Research output: Contribution to Journal/Magazine › Journal article › peer-review
Research output: Contribution to Journal/Magazine › Journal article › peer-review
}
TY - JOUR
T1 - Voltage noise thermometry in integrated circuits at millikelvin temperatures
AU - Ridgard, George
AU - Thompson, Michael
AU - Schreckenberg, Lea
AU - Deshpande, Nihal
AU - Cabrera-Galicia, Alfonso
AU - Bourgeois, Olivier
AU - Doebele, Victor
AU - Prance, Jonathan
PY - 2025/6/23
Y1 - 2025/6/23
N2 - This paper demonstrates the use of voltage noise thermometry, with a cross-correlation technique, as a dissipation-free method of thermometry inside a CMOS integrated circuit (IC). We show that this technique exhibits broad agreement with the refrigerator temperature range from 300 mK to 8 K. Furthermore, it shows substantial agreement with both an independent in-IC thermometry technique and a simple thermal model as a function of power dissipation inside the IC. As the device under a test is a resistor, it is feasible to extend this technique by placing many resistors in an IC to monitor the local temperatures, without increasing IC design complexity. This could lead to better understanding of the thermal profile of ICs at cryogenic temperatures. This has its greatest potential application in quantum computing, where the temperature at the cold classical-quantum boundary must be carefully controlled to maintain qubit performance.
AB - This paper demonstrates the use of voltage noise thermometry, with a cross-correlation technique, as a dissipation-free method of thermometry inside a CMOS integrated circuit (IC). We show that this technique exhibits broad agreement with the refrigerator temperature range from 300 mK to 8 K. Furthermore, it shows substantial agreement with both an independent in-IC thermometry technique and a simple thermal model as a function of power dissipation inside the IC. As the device under a test is a resistor, it is feasible to extend this technique by placing many resistors in an IC to monitor the local temperatures, without increasing IC design complexity. This could lead to better understanding of the thermal profile of ICs at cryogenic temperatures. This has its greatest potential application in quantum computing, where the temperature at the cold classical-quantum boundary must be carefully controlled to maintain qubit performance.
U2 - 10.1063/5.0268728
DO - 10.1063/5.0268728
M3 - Journal article
VL - 137
JO - Journal of Applied Physics
JF - Journal of Applied Physics
SN - 0021-8979
IS - 24
M1 - 245901
ER -