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Professor Andrew Richardson

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  1. 1999
  2. Published

    The application of neuMOS transistors to enhanced Built-in Self-Test (BIST) and product quality

    Richardson, A. & Nicholson, R., 18/06/1999, p. 257-261. 5 p.

    Research output: Contribution to conference - Without ISBN/ISSN › Conference paper › peer-review

  3. Published

    Fault simulation for MEMS

    Rosing, R., Richardson, A., Dorey, A. & Peyton, A., 1/06/1999, Intelligent and Self-Validating Sensors (Ref. No. 1999/160), IEE Colloquium on. p. 7/1 -7/6

    Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Conference contribution/Paper › peer-review

  4. Published

    A digital partial built-in self-test structure for a high performance automatic gain control circuit

    Lechner, A., Ferguson, J., Richardson, A. & Hermes, B., 1999, DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION 1999, PROCEEDINGS. Borrione, D. & Ernst, R. (eds.). LOS ALAMITOS: IEEE COMPUTER SOC, p. 232-238 7 p.

    Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Conference contribution/Paper › peer-review

  5. 1998
  6. Published

    An Integrated Diagnostic Reconfiguration (IDR) design approach for fault tolerant mixed signal integrated systems

    Richardson, A., Sharif, E. & Dorey, A., 11/06/1998, p. 88-90. 3 p.

    Research output: Contribution to conference - Without ISBN/ISSN › Conference paper

  7. Published

    A design for testability study on a high performance automatic gain control circuit.

    Lechner, A., Richardson, A. M. D., Hermes, B. & Ohletz, M., 1998, Proceedings of the 16th IEEE VLSI test symposium. IEEE, p. 376-385 10 p.

    Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

  8. Published

    An approach to realistic fault prediction and layout design for testability in analog circuits

    Prieto, J. A., Rueda, A., Grout, I., Peralias, E., Huertas, J. L. & Richardson, A. M. D., 1998, Design, Automation and Test in Europe, 1998 Proceedings. LOS ALAMITOS: IEEE COMPUTER SOC, p. 905-909 5 p.

    Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Conference contribution/Paper › peer-review

  9. Published

    An approach to realistic fault prediction and layout design for testability in analogue circuits.

    Prieto, J., Richardson, A. M. D., Rueda, A. & Grout, I., 1998, Proceedings of the conference on design, automation and test in Europe. Paris, p. 906-912 7 p.

    Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

  10. Published

    An integrated diagnostic reconfiguration (IDR) technique for fault tolerant mixed signal microsystems.

    Sharif, E., Dorey, A. P. & Richardson, A. M. D., 1998, Proceedings of the IEEE international circuits and systems symposium. IEEE

    Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

  11. Published

    Clock switching: a new design for current test (DcT) method for dynamic logic circuits

    Rosing, R., Richardson, A. M. D., Kerkhoff, A. & Acosta, A., 1998, IDDQ Testing, 1998. Proceedings. 1998 IEEE International Workshop on. IEEE, p. 20-25 6 p.

    Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Conference contribution/Paper › peer-review

  12. Published

    Design for testability strategies for a high performance gain control circuit.

    Lechner, A., Richardson, A. M. D., Hermes, B. & Perkins, A., 1998, Proceedings of the international IEEE mixed signal test workshop. The Hague

    Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

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