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Research

Dr Roshan Weerasekera

Formerly at Lancaster University

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  1. Published

    Exploration of Through Silicon Via Interconnect Parasitics for 3-Dimensional Integrated Circuits

    Grange, M., Weerasekera, R., Pamunuwa, D. & Tenhunen, H., 2009, Workshop Notes, Design, Automation and Test in Europe (DATE). Nice

    Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

  2. Published

    Physical Mapping and Performance Study of a Multi-Clock 3-Dimensional Network-on-Chip Mesh.

    Grange, M., Weldezion, A. Y., Pamunuwa, D. B., Weerasekera, R., Zhonghai, L., Jantsch, A. & Shippen, D., 2009, Proceedings of the IEEE International Conference on 3D System Integration (3D IC), 2009. San Francisco: IEEE

    Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

  3. Published

    Nanodevices : from novelty toys to functional devices - an integration perspective.

    Pamunuwa, D. & Weerasekera, R., 08/2006, Proceedings of the IEEE international conference on industrial and information systems.. p. 103 -108

    Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

  4. Published

    Crosstalk immune interconnect driver design.

    Weerasekera, R., Pamunuwa, D. B., Zheng, L. R. & Tenhunen, H., 2004, Proceedings of the international symposium on system-on-chip conference. p. 139-142 4 p.

    Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

  5. Published

    2-D and 3-D Integration of Heterogeneous Electronic Systems under Cost, Performance and Technological Constraints

    Weerasekera, R., Pamunuwa, D., Zheng, L-R. & Tenhunen, H., 08/2009, In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 28, 8, p. 1237-1250 14 p.

    Research output: Contribution to Journal/Magazine › Journal article

  6. Published

    Minimal-power, delay-balanced smart repeaters for global interconnects in the nanometer regime.

    Weerasekera, R., Pamunuwa, D. B., Zheng, L-R. & Tenhunen, H., 05/2008, In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 16, 5, p. 589-593 5 p.

    Research output: Contribution to Journal/Magazine › Journal article › peer-review

  7. Published

    Closed-form equations for through-silicon via (TSV) parasitics in 3-D integrated circuits (ICs).

    Weerasekera, R., Pamunuwa, D. B., Grange, M., Tenhunen, H. & Zheng, L-R., 2009, Workshop Notes, Design, Automation and Test in Europe (DATE). Nice

    Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

  8. Published

    Extending systems-on-chip to the third dimension : performance, cost and technological tradeoffs.

    Weerasekera, R., Zheng, L-R., Pamunuwa, D. B. & Tenhunen, H., 11/2007, Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD). San Jose, California: IEEE, p. 212-219 8 p.

    Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

  9. Published

    Early selection of system implementation choice among SoC, SoP and 3-D integration.

    Weerasekera, R., Zheng, L-R., Pamunuwa, D. B. & Tenhunen, H., 09/2007, Proc. International System-On-Chip Conference (SOCC). Hsin Chu, Taiwan: IEEE

    Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

  10. Published

    Delay-balanced smart repeaters for on-chip global signaling.

    Weerasekera, R., Pamunuwa, D. B., Zheng, L-R. & Tenhunen, H., 12/02/2007, Proc. International Conference on VLSI Design. Bangalore: IEEE, p. 308-313 6 p.

    Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

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