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Dr Dinesh Pamunuwa

Formerly at Lancaster University

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  1. 2005
  2. Published

    Switching sensitive driver circuit to combat dynamic delay in on-chip buses

    Weerasekera, R., Zheng, L.-R., Pamunuwa, D. B., Tenhunen, H., Paliouras, V. (Editor), Vounckx, J. (Editor) & Verkest, D. (Editor), 09/2005, Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation: 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005. Proceedings. Paliouras, V., Vounckx, J. & Verkest, D. (eds.). Berlin: Springer, p. 277-285 9 p. (Lecture Notes in Computer Science; vol. 3728).

    Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

  3. 2004
  4. Published

    A study on the implementation of 2-D mesh-based networks-on-chip in the nanometre regime.

    Pamunuwa, D. B., Öberg, J., Millberg, M., Zheng, L.-R., Jantsch, A. & Tenhunen, H., 1/10/2004, In: Integration, the VLSI Journal. 38, 1, p. 3-17 15 p.

    Research output: Contribution to Journal/Magazine › Journal article › peer-review

  5. Published

    Crosstalk immune interconnect driver design.

    Weerasekera, R., Pamunuwa, D. B., Zheng, L. R. & Tenhunen, H., 2004, Proceedings of the international symposium on system-on-chip conference. p. 139-142 4 p.

    Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

  6. 2003
  7. Published

    Maximizing throughput over parallel wire structures in the deep submicrometer regime.

    Pamunuwa, D. B., Tenhunen, H. & Zheng, L., 1/04/2003, In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 11, 2, p. 224-243 20 p.

    Research output: Contribution to Journal/Magazine › Journal article › peer-review

  8. Published

    Modelling noise and delay in VLSI circuits.

    Pamunuwa, D. B., Elassaad, S. & Tenhunen, H., 02/2003, In: Electronics Letters. 39, 3, p. 269-271 3 p.

    Research output: Contribution to Journal/Magazine › Journal article › peer-review

  9. Published

    A global wire planning scheme for Network-on-Chip.

    Liu, J., Zheng, L.-R., Pamunuwa, D. B. & Tenhunen, H., 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03.. Vol. 4. p. IV-892-IV-895

    Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

  10. Published

    Analytic modeling of interconnects for deep submicron circuits.

    Pamunuwa, D. B., Elassaad, S. & Tenhunen, H., 2003, 2003 International Conference on Computer-Aided Design (ICCAD'03). San Jose, California: IEEE Computer Society, p. 835-842 8 p.

    Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

  11. Published

    Closed form metrics to accurately model the response in general arbitrarily-coupled RC trees.

    Pamunuwa, D. B. & Elassaad, S., 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03.. IEEE, Vol. 4. p. IV-604

    Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

  12. Published

    Layout, performance and power trade-offs in mesh-based network-on chip architectures.

    Pamunuwa, D. B., Öberg, J., Zheng, L.-R., Millberg, M., Jantsch, A. & Tenhunen, H., 2003, Proc. IFIP International Conference on VLSI Systems-on-chip. Darmstadt, Germany: Technische Universität Darmstadt, Insitute of Microelectronic Systems, p. 362-366 5 p.

    Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

  13. Published

    Modelling and analysis of interconnects for deep submicron systems-on-chip.

    Pamunuwa, D. B., 2003, Stockholm: Royal Institute of Technology.

    Research output: Book/Report/Proceedings › Book

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