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  1. Published

    Minimal-power, delay-balanced smart repeaters for global interconnects in the nanometer regime.

    Weerasekera, R., Pamunuwa, D. B., Zheng, L-R. & Tenhunen, H., 05/2008, In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 16, 5, p. 589-593 5 p.

    Research output: Contribution to Journal/Magazine › Journal article › peer-review

  2. Published

    Closed-form equations for through-silicon via (TSV) parasitics in 3-D integrated circuits (ICs).

    Weerasekera, R., Pamunuwa, D. B., Grange, M., Tenhunen, H. & Zheng, L-R., 2009, Workshop Notes, Design, Automation and Test in Europe (DATE). Nice

    Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

  3. Published

    Extending systems-on-chip to the third dimension : performance, cost and technological tradeoffs.

    Weerasekera, R., Zheng, L-R., Pamunuwa, D. B. & Tenhunen, H., 11/2007, Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD). San Jose, California: IEEE, p. 212-219 8 p.

    Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

  4. Published

    Early selection of system implementation choice among SoC, SoP and 3-D integration.

    Weerasekera, R., Zheng, L-R., Pamunuwa, D. B. & Tenhunen, H., 09/2007, Proc. International System-On-Chip Conference (SOCC). Hsin Chu, Taiwan: IEEE

    Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

  5. Published

    Delay-balanced smart repeaters for on-chip global signaling.

    Weerasekera, R., Pamunuwa, D. B., Zheng, L-R. & Tenhunen, H., 12/02/2007, Proc. International Conference on VLSI Design. Bangalore: IEEE, p. 308-313 6 p.

    Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

  6. Published

    Minimal-power, delay-balanced smart repeaters for interconnects in the nanometer regime.

    Weerasekera, R., Pamunuwa, D. B., Zheng, L-R. & Tenhunen, H., 03/2006, Proc. International Workshop on System-level Interconnect Prediction (SLIP). Munich: ACM, p. 113-120 8 p.

    Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

  7. Published

    On signalling over through-silicon via (TSV) interconnects in 3-D integrated circuits.

    Weerasekera, R., Grange, M., Pamunuwa, D. B. & Tenhunen, H., 03/2010, p. 1325-1328. 4 p.

    Research output: Contribution to conference - Without ISBN/ISSN › Conference paper › peer-review

  8. Published

    Compact modelling of through-silicon vias (TSVs) in three-dimensional (3-D) integrated circuits.

    Weerasekera, R., Grange, M., Pamunuwa, D. B., Tenhunen, H. & Zheng, L-R., 10/2009, Proceedings of the IEEE International Conference on 3D System Integration (3D IC), 2009. San Francisco: IEEE

    Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

  9. Published

    Switching sensitive driver circuit to combat dynamic delay in on-chip buses

    Weerasekera, R., Zheng, L-R., Pamunuwa, D. B., Tenhunen, H., Paliouras, V. (ed.), Vounckx, J. (ed.) & Verkest, D. (ed.), 09/2005, Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation: 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005. Proceedings. Paliouras, V., Vounckx, J. & Verkest, D. (eds.). Berlin: Springer, p. 277-285 9 p. (Lecture Notes in Computer Science; vol. 3728).

    Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

  10. Published

    Amplitude stabilization and active control of a terahertz quantum cascade laser with a graphene loaded split-ring-resonator array

    Wei, B., Kindness, S., Almond, N., Wallis, R., Wu, Y., Ren, Y., Shi, S. C., Braeuninger-Weimer, P., Hofmann, S., Beere, H. E., Ritchie, D. & Degl'Innocenti, R., 15/05/2018, In: Applied Physics Letters. 112, 20, 4 p., 201102.

    Research output: Contribution to Journal/Magazine › Journal article › peer-review

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