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Professor Andrew Richardson

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2001
Published
A failure mode analysis of a 6-bit folding ADCs.
Lechner, A., Richardson, A. M. D., Burbidge, M. & Hermes, B., 2001, Proceedings of the 7th IEEE international mixed-signal testing workshop (IMSTW ’01). p. 19-23 5 p.
Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter
Published
Finite element analysis to support component level fault modelling for MEMS.
Reichenbach, R., Rosing, R., Richardson, A. M. D. & Dorey, A. P., 2001, Proceedings of SPIE design, test, integration and packaging of MEMS symposium. Vol. 4408. p. 147-158 12 p.
Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter
Published
Generation of component level fault models for MEMS.
Rosing, R., Reichenbach, R., Richardson, A. M. D. & Dorey, A. P., 2001, Proceedings of the 7th international mixed-signal testing workshop (IMSTW ’01). p. 40-45 6 p.
Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter
Published
Short circuit faults in state-of-the-art ADCs – are they hard or soft?
Lechner, A., Richardson, A. M. D. & Hermes, B., 2001, 10th Asian Test Symposium : proceedings : 19-21 November, 2001, Kyoto, Japan. IEEE Computer Society, p. 417-422 6 p.
Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter
Published
Simple digital only test approach for embedded charge-pump phase-locked loops.
Burbidge, M. & Richardson, A. M. D., 2001, In: Electronics Letters. 37, 22, p. 1318-1319 2 p.
Research output: Contribution to Journal/Magazine › Journal article
Published
Test techniques for embedded charge pump phase-locked loops: problems, current BIST techniques and alternative suggestions.
Burbidge, M., Richardson, A. M. D. & Lechner, A., 2001, Proceedings of the 7th IEEE international test workshop. p. 97-102 6 p.
Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter
Published
Towards a better understanding of failure modes and test requirements of ADCs.
Lechner, A., Richardson, A. M. D. & Hermes, B., 2001, Proceedings of a conference: automation and test in Europe (DATE ’01). p. 803
Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter
2000
Published
A built-in test solution for a SMART silicon micromachined resonant pressure sensor.
Jeffery, C., Rosing, R. & Richardson, A. M. D., 2000, IEEE European Test Workshop. IEEE
Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter
Published
A fault simulation methodology for MEMS.
Rosing, R., Richardson, A. M. D. & Dorey, A. P., 2000, Proceedings of the design automation and test in Europe conference. Paris: IEEE, p. 476-483 8 p.
Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter
Published
A fault simulation methodology for MEMS.
Rosing, R., Richardson, A. M. D. & Dorey, A. P., 2000, Proceedings of the IEE symposium on quality and automation (RESQUA 2000). Penang, Malaysia
Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter
Published
Applications of mixed signal test strategies to next generation microsystems.
Jeffery, C., Rosing, R. & Richardson, A. M. D., 2000, Design, modeling, and simulation in microelectronics. 4228 ed. SPIE (Society of Photo-Optical Instrumentation Engineers), p. 21-32 12 p.
Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter
Published
Design-for-testability for mixed signal and analogue design.
Richardson, A. M. D. & Lechner, A., 2000, Proceedings of 7th international conference on mixed design of integrated circuits and systems. Poland
Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter
Published
Fault simulation and modelling of microelectromechanical systems.
Rosing, R., Lechner, A., Richardson, A. M. D. & Dorey, A. P., 2000, In: IEE Journal on Computing and Control Engineering. 11, 5, p. 242-250 9 p.
Research output: Contribution to Journal/Magazine › Journal article
1999
Published
Reconfiguration based built-in self-test for analogue front-end circuits
Richardson, A., Lechner, A. & Hermes, B., 18/06/1999, p. 243-247. 5 p.
Research output: Contribution to conference - Without ISBN/ISSN › Conference paper › peer-review
Published
Test support strategies for MEMS
Richardson, A., Rosing, R., Peyton, A. & Dorey, A., 18/06/1999, p. 345-350. 6 p.
Research output: Contribution to conference - Without ISBN/ISSN › Conference paper › peer-review
Published
The application of neuMOS transistors to enhanced Built-in Self-Test (BIST) and product quality
Richardson, A. & Nicholson, R., 18/06/1999, p. 257-261. 5 p.
Research output: Contribution to conference - Without ISBN/ISSN › Conference paper › peer-review
Published
Fault simulation for MEMS
Rosing, R., Richardson, A., Dorey, A. & Peyton, A., 1/06/1999, Intelligent and Self-Validating Sensors (Ref. No. 1999/160), IEE Colloquium on. p. 7/1 -7/6
Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Conference contribution/Paper › peer-review
Published
A digital partial built-in self-test structure for a high performance automatic gain control circuit
Lechner, A., Ferguson, J., Richardson, A. & Hermes, B., 1999, DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION 1999, PROCEEDINGS. Borrione, D. & Ernst, R. (eds.). LOS ALAMITOS: IEEE COMPUTER SOC, p. 232-238 7 p.
Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Conference contribution/Paper › peer-review
1998
Published
An Integrated Diagnostic Reconfiguration (IDR) design approach for fault tolerant mixed signal integrated systems
Richardson, A., Sharif, E. & Dorey, A., 11/06/1998, p. 88-90. 3 p.
Research output: Contribution to conference - Without ISBN/ISSN › Conference paper
Published
A design for testability study on a high performance automatic gain control circuit.
Lechner, A., Richardson, A. M. D., Hermes, B. & Ohletz, M., 1998, Proceedings of the 16th IEEE VLSI test symposium. IEEE, p. 376-385 10 p.
Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter
Published
An approach to realistic fault prediction and layout design for testability in analog circuits
Prieto, J. A., Rueda, A., Grout, I., Peralias, E., Huertas, J. L. & Richardson, A. M. D., 1998, Design, Automation and Test in Europe, 1998 Proceedings. LOS ALAMITOS: IEEE COMPUTER SOC, p. 905-909 5 p.
Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Conference contribution/Paper › peer-review
Published
An approach to realistic fault prediction and layout design for testability in analogue circuits.
Prieto, J., Richardson, A. M. D., Rueda, A. & Grout, I., 1998, Proceedings of the conference on design, automation and test in Europe. Paris, p. 906-912 7 p.
Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter
Published
An integrated diagnostic reconfiguration (IDR) technique for fault tolerant mixed signal microsystems.
Sharif, E., Dorey, A. P. & Richardson, A. M. D., 1998, Proceedings of the IEEE international circuits and systems symposium. IEEE
Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter
Published
Clock switching: a new design for current test (DcT) method for dynamic logic circuits
Rosing, R., Richardson, A. M. D., Kerkhoff, A. & Acosta, A., 1998, IDDQ Testing, 1998. Proceedings. 1998 IEEE International Workshop on. IEEE, p. 20-25 6 p.
Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Conference contribution/Paper › peer-review
Published
Design for testability strategies for a high performance gain control circuit.
Lechner, A., Richardson, A. M. D., Hermes, B. & Perkins, A., 1998, Proceedings of the international IEEE mixed signal test workshop. The Hague
Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

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Research

Professor Andrew Richardson

A failure mode analysis of a 6-bit folding ADCs.

Finite element analysis to support component level fault modelling for MEMS.

Generation of component level fault models for MEMS.

Short circuit faults in state-of-the-art ADCs – are they hard or soft?

Simple digital only test approach for embedded charge-pump phase-locked loops.

Test techniques for embedded charge pump phase-locked loops: problems, current BIST techniques and alternative suggestions.

Towards a better understanding of failure modes and test requirements of ADCs.

A built-in test solution for a SMART silicon micromachined resonant pressure sensor.

A fault simulation methodology for MEMS.

A fault simulation methodology for MEMS.

Applications of mixed signal test strategies to next generation microsystems.

Design-for-testability for mixed signal and analogue design.

Fault simulation and modelling of microelectromechanical systems.

Reconfiguration based built-in self-test for analogue front-end circuits

Test support strategies for MEMS

The application of neuMOS transistors to enhanced Built-in Self-Test (BIST) and product quality

Fault simulation for MEMS

A digital partial built-in self-test structure for a high performance automatic gain control circuit

An Integrated Diagnostic Reconfiguration (IDR) design approach for fault tolerant mixed signal integrated systems

A design for testability study on a high performance automatic gain control circuit.

An approach to realistic fault prediction and layout design for testability in analog circuits

An approach to realistic fault prediction and layout design for testability in analogue circuits.

An integrated diagnostic reconfiguration (IDR) technique for fault tolerant mixed signal microsystems.

Clock switching: a new design for current test (DcT) method for dynamic logic circuits

Design for testability strategies for a high performance gain control circuit.

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